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Home › Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR)

Method to compress responses of automatic test pattern generation (ATPG) vectors into an on-chip multiple-input shift register (MISR)

US Patent 10969433 · Granted Apr 6, 2021

Estimated economic value: $69,722,000 ⓘ

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