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Home › Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods

Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods

US Patent 10411091 · Granted Sep 10, 2019

Estimated economic value: $12,596,000 ⓘ

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