Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6628138 | Increasing decoupling capacitance using preferential shields | Sudhakar Bobba | 2003-09-30 |
| 6617699 | 120 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Dean Liu | 2003-09-09 |
| 6618845 | Verifying on-chip decoupling capacitance | Pradeep Trivedi, Dean Liu | 2003-09-09 |
| 6618277 | Apparatus for reducing the supply noise near large clock drivers | Claude Gauthier, Brian Amick, Pradeep Trivedi, Dean Liu | 2003-09-09 |
| 6611573 | Non-integer division of frequency | Pradeep Trivedi, Dean Liu | 2003-08-26 |
| 6604226 | Verifying on-chip decoupling capacitance using transistor and capacitor surface area information | Devendra Vidhani | 2003-08-05 |
| 6577002 | 180 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Pradeep Trivedi | 2003-06-10 |
| 6566758 | Current crowding reduction technique for flip chip package technology | Pradeep Trivedi, Sudhakar Bobba, Dean Liu | 2003-05-20 |
| 6563336 | Signal shielding assignment technique for precharge based logic | Sudhakar Bobba | 2003-05-13 |
| 6549038 | Method of high-performance CMOS design | Carl Sechen, Larry E. McMurchie, Gin Yee | 2003-04-15 |
| 6541873 | 90 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Dean Liu | 2003-04-01 |
| 6515527 | Method for smoothing dI/dT noise due to clock transitions | Brian Amick, Dean Liu | 2003-02-04 |
| 6501328 | Method for reducing peak to peak jitter in a dual-loop delay locked loop | Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi | 2002-12-31 |
| 6495926 | 60 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Dean Liu | 2002-12-17 |
| 6483341 | CMOS-microprocessor chip and package anti-resonance apparatus | Claude Gauthier, Richard L. Wheeler, Brian Amick | 2002-11-19 |
| 6476663 | Method for reducing supply noise near an on-die thermal sensor | Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi | 2002-11-05 |
| 6473883 | Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid | Sudhakar Bobba | 2002-10-29 |
| 6456107 | CMOS-microprocessor chip and package anti-resonance method | Claude Gauthier, Richard L. Wheeler, Brian Amick | 2002-09-24 |
| 6441640 | CMOS-microprocessor chip and package anti-resonance pass-band shunt apparatus | Claude Gauthier, Brian Amick, Richard L. Wheeler | 2002-08-27 |