Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9599645 | High speed clock cycle rate digital voltage monitor with triggered tracing for integrated circuits | — | 2017-03-21 |
| 9507405 | System and method for managing power in a chip multiprocessor using a proportional feedback mechanism | Venkatram Krishnaswamy, Georgios Konstadinidis, Yifan YangGong | 2016-11-29 |
| 9483603 | Micro-benchmark analysis optimization for microprocessor designs | Haowei Zhang, Xiaoying Shen | 2016-11-01 |
| 9312864 | AFLL with increased timing margin | Yifan YangGong, Changku Hwang, Daniel S. Woo | 2016-04-12 |
| 9285865 | Dynamic link scaling based on bandwidth utilization | Brian F. Keish, Thomas M. Wicki | 2016-03-15 |
| 8990606 | Constant frequency architectural timer in a dynamic clock domain | Ali Vahidsafa | 2015-03-24 |
| 8949651 | Multiple clock domain cycle skipping utilizing optimal mask to minimize voltage noise | — | 2015-02-03 |
| 8729947 | Wide-range glitch-free asynchronous clock switch | Changku Hwang, Daisy Jian, Ali Vahidsafa | 2014-05-20 |
| 8604852 | Noise suppression using an asymmetric frequency-locked loop | Changku Hwang, Daniel S. Woo, Yifan YangGong | 2013-12-10 |
| 8332729 | System and method for automatic communication lane failover in a serial link | Ramaswamy Sivaramakrishnan, Stephen E. Phillips | 2012-12-11 |
| 8269544 | Power-supply noise suppression using a frequency-locked loop | David Greenhill, Robert P. Masleid, Georgios Konstadinidis, King Yen | 2012-09-18 |
| 8261019 | Conveying critical data in a multiprocessor system | Sumti Jairath | 2012-09-04 |
| 7764717 | Rapid datarate estimation for a data stream multiplexer | James Yu, Aly E. Orady | 2010-07-27 |
| 7333468 | Digital phase locked loops for packet stream rate matching and restamping | Aly E. Orady, James Yu, Andrew Yang | 2008-02-19 |