Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6055616 | System for efficient implementation of multi-ported logic FIFO structures in a processor | — | 2000-04-25 |
| 6052777 | Method for delivering precise traps and interrupts in an out-of-order processor | — | 2000-04-18 |
| 6052775 | Method for non-intrusive cache fills and handling of load misses | Ricky C. Hetherington | 2000-04-18 |
| 6049868 | Apparatus for delivering precise traps and interrupts in an out-of-order processor | — | 2000-04-11 |
| 6035374 | Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency | Joseph I. Chamdani | 2000-03-07 |
| 6006326 | Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies | Ricky C. Hetherington | 1999-12-21 |
| 5999727 | Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions | Ricky C. Hetherington | 1999-12-07 |
| 5987594 | Apparatus for executing coded dependent instructions having variable latencies | Ricky C. Hetherington | 1999-11-16 |
| 5978898 | Allocating registers in a superscalar machine | Robert Hathaway | 1999-11-02 |
| 5978864 | Method for thermal overload detection and prevention for an intergrated circuit processor | Ricky C. Hetherington | 1999-11-02 |
| 5964869 | Instruction fetch mechanism with simultaneous prediction of control-flow instructions | Adam R. Talcott | 1999-10-12 |
| 5958047 | Method for precise architectural update in an out-of-order processor | Arjun Prabhu | 1999-09-28 |
| 5948106 | System for thermal overload detection and prevention for an integrated circuit processor | Ricky C. Hetherington | 1999-09-07 |
| 5941977 | Apparatus for handling register windows in an out-of-order processor | Dani Y. Dakhil | 1999-08-24 |
| 5941985 | Branch instruction prediction method | Adam R. Talcott | 1999-08-24 |
| 5935238 | Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles | Adam R. Talcott | 1999-08-10 |
| 5930819 | Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache | Ricky C. Hetherington, Sharad Mehrotra | 1999-07-27 |
| 5898853 | Apparatus for enforcing true dependencies in an out-of-order processor | Dani Y. Dakhil | 1999-04-27 |
| 5890008 | Method for dynamically reconfiguring a processor | Ricky C. Hetherington | 1999-03-30 |
| 5884070 | Method for processing single precision arithmetic operations in system where two single precision registers are aliased to one double precision register | — | 1999-03-16 |
| 5880978 | Method and apparatus for creating an output vector from an input vector | Ralph Portillo, Naveen Krishnamurthy | 1999-03-09 |
| 5875316 | Method for handling complex instructions in an out-of-order processor | Dani Y. Dakhil | 1999-02-23 |
| 5870597 | Method for speculative calculation of physical register addresses in an out of order processor | Dani Y. Dakhil | 1999-02-09 |
| 5860018 | Method for tracking pipeline resources in a superscalar processor | — | 1999-01-12 |
| 5857098 | Branch instruction prediction apparatus | Adam R. Talcott | 1999-01-05 |