Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7305492 | Content service aggregation system | Mark Bryers, Elango Ganesan, Frederick Gruner, David T. Hass, Robert Hathaway +11 more | 2007-12-04 |
| 6920542 | Application processing employing a coprocessor | Frederick Gruner, Robert Hathaway, Elango Ganesan, Nazar Zaidi | 2005-07-19 |
| 6901482 | Managing ownership of a full cache line using a store-create operation | Fred Gruner, David T. Hass, Robert Hathaway, Ricardo Ramirez, Nazar Zaidi | 2005-05-31 |
| 6898673 | Co-processor including a media access controller | Frederick Gruner, Robert Hathaway, Elango Ganesan, Nazar Zaidi | 2005-05-24 |
| 6895477 | Ring-based memory requests in a shared memory multi-processor | David T. Hass, Frederick Gruner, Nazar Zaidi, Mark Vilas | 2005-05-17 |
| 6892282 | Ring based multi-processing system | David T. Hass, Mark Vilas, Frederick Gruner, Nazar Zaidi | 2005-05-10 |
| 6880049 | Sharing a second tier cache memory in a multi-processor | Fred Gruner, David T. Hass, Nazar Zaidi | 2005-04-12 |
| 6745289 | Processing packets in cache memory | Frederick Gruner, Elango Ganesan, Nazar Zaidi | 2004-06-01 |
| 6289441 | Method and apparatus for performing multiple branch predictions per cycle | Adam R. Talcott, Rajasekhar Cherabuddi, Sanjay Patel | 2001-09-11 |
| 6256709 | Method for storing data in two-way set associative odd and even banks of a cache memory | Sanjay Patel, Rajasekhar Cherabuddi, Adam R. Talcott | 2001-07-03 |
| 6256729 | Method and apparatus for resolving multiple branches | Rajasekhar Cherabuddi, Sanjay Patel, Adam R. Talcott | 2001-07-03 |
| 6240502 | Apparatus for dynamically reconfiguring a processor | Ricky C. Hetherington | 2001-05-29 |
| 6219723 | Method and apparatus for moderating current demand in an integrated circuit processor | Ricky C. Hetherington | 2001-04-17 |
| 6219778 | Apparatus for generating out-of-order results and out-of-order condition codes in a processor | Arjun Prabhu | 2001-04-17 |
| 6154812 | Method for inhibiting thrashing in a multi-level non-blocking cache system | Ricky C. Hetherington, Sharad Mehrotra | 2000-11-28 |
| 6148371 | Multi-level non-blocking cache system with inhibiting thrashing | Ricky C. Hetherington, Sharad Mehrotra | 2000-11-14 |
| 6144982 | Pipeline processor and computing system including an apparatus for tracking pipeline resources | — | 2000-11-07 |
| 6105128 | Method and apparatus for dispatching instructions to execution units in waves | Robert Hathaway | 2000-08-15 |
| 6098165 | Fetching and handling a bundle of instructions comprising instructions and non-complex instructions | Dani Y. Dakhil | 2000-08-01 |
| 6094719 | Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers | — | 2000-07-25 |
| 6085305 | Apparatus for precise architectural update in an out-of-order processor | Arjun Prabhu | 2000-07-04 |
| 6081873 | In-line bank conflict detection and resolution in a multi-ported non-blocking cache | Ricky C. Hetherington, Sharad Mehrotra | 2000-06-27 |
| 6075931 | Method for efficient implementation of multi-ported logic FIFO structures in a processor | — | 2000-06-13 |
| 6058472 | Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine | P. Chidambaran, Ricky C. Hetherington | 2000-05-02 |
| 6058466 | System for allocation of execution resources amongst multiple executing processes | Joseph I. Chamdani | 2000-05-02 |