Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6066959 | Logic array having multi-level logic planes | Frederick Gruner | 2000-05-23 |
| 6034543 | Programmable logic array structure having reduced parasitic loading | Jian Hui Huang, Fredrick R. Gruner | 2000-03-07 |
| 5977794 | Logic array having interleaved logic planes | Frederick Gruner | 1999-11-02 |
| 5880978 | Method and apparatus for creating an output vector from an input vector | Ramesh Panwar, Naveen Krishnamurthy | 1999-03-09 |