Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6487715 | Dynamic code motion optimization and path tracing | Joseph I. Chamdani, William L. Lynch | 2002-11-26 |
| 6351808 | Vertically and horizontally threaded processor with multidimensional storage for storing thread data | William N. Joy, Marc Tremblay, Joseph I. Chamdani | 2002-02-26 |
| 6341347 | Thread switch logic in a multiple-thread processor | William N. Joy, Marc Tremblay, Joseph I. Chamdani | 2002-01-22 |
| 6317810 | Microprocessor having a prefetch cache | Herbert Lopez-Aguado, Denise Chiacchia, William L. Lynch | 2001-11-13 |
| 6272602 | Multiprocessing system employing pending tags to maintain cache coherence | Ashok Singhal, Alan Yamauchi | 2001-08-07 |
| 6138212 | Apparatus and method for generating a stride used to derive a prefetch address | Denise Chiacchia, Herbert Lopez-Aguado | 2000-10-24 |
| 6098154 | Apparatus and method for generating a stride used to derive a prefetch address | Herbert Lopez-Aguado, Denise Chiacchia | 2000-08-01 |
| 6044446 | Mechanism to reduce interprocessor traffic in a shared memory multi-processor computer system | Bill Joy | 2000-03-28 |
| 6035118 | Mechanism to eliminate the performance penalty of computed jump targets in a pipelined processor | Kit S. Tam | 2000-03-07 |
| 6016532 | Method for handling data cache misses using help instructions | William L. Lynch | 2000-01-18 |
| 5996061 | Method for invalidating data identified by software compiler | Herbert Lopez-Aguado, Denise Chiacchia | 1999-11-30 |
| 5964862 | Execution unit and method for using architectural and working register files to reduce operand bypasses | Arthur T. Leung | 1999-10-12 |
| 5958041 | Latency prediction in a pipelined microarchitecture | Joseph Anthony Petolino, Jr., William L. Lynch, Chitresh Narasimhaiah | 1999-09-28 |
| 5948098 | Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines | Arthur T. Leung | 1999-09-07 |
| 5912906 | Method and apparatus for recovering from correctable ECC errors | Chang-Hong Wu | 1999-06-15 |
| 5898852 | Load instruction steering in a dual data cache microarchitecture | Joseph Anthony Petolino, Jr., William L. Lynch, Kalon S. Holdbrook | 1999-04-27 |
| 5878252 | Microprocessor configured to generate help instructions for performing data cache fills | William L. Lynch | 1999-03-02 |
| 5754819 | Low-latency memory indexing method and structure | William L. Lynch | 1998-05-19 |
| 5712791 | Method and apparatus for designing a circuit by analyzing selected artificial hardware dependencies inserted into a dynamic dependency graph | — | 1998-01-27 |
| RE32101 | Weigh feeding apparatus | Ronald J. Ricciardi, Angelo Ferrara, Joseph L. Hartmann | 1986-04-01 |
| 4320855 | Weigh feeding apparatus | Ronald J. Ricciardi, Angelo Ferrara, Joseph L. Hartmann | 1982-03-23 |