Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7487327 | Processor and method for device-specific memory address translation | Bruce J. Chang, Ricky C. Hetherington, Brian J. McGee, David M. Kahn | 2009-02-03 |
| 7444503 | Method and apparatus for delivering device drivers | David J. Redman, Gregory Onufer, John G. Johnson | 2008-10-28 |
| 7430643 | Multiple contexts for efficient use of translation lookaside buffer | Paul J. Jordan, William J. Kucharski, Roman Zajcew, Quinn A. Jacobson | 2008-09-30 |
| 7331043 | Detecting and mitigating soft errors using duplicative instructions | — | 2008-02-12 |
| 7290116 | Level 2 cache index hashing to avoid hot spots | Greg F. Grohoski, Manish K. Shah, John D. Davis, Cong Fu, Venkatesh Iyengar +2 more | 2007-10-30 |
| 7191292 | Logging of level-two cache transactions into banks of the level-two cache for system rollback | Shailender Chaudhry, Quinn A. Jacobson | 2007-03-13 |
| 7178005 | Efficient implementation of timers in a multithreaded processor | Paul J. Jordan, John G. Johnson | 2007-02-13 |
| 7124160 | Processing architecture having parallel arithmetic capability | Daniel S. Rice | 2006-10-17 |
| 7080365 | Method and apparatus for simulation system compiler | Jeffrey M. Broughton, Liang T. Chen, William Lam, Derek Pappas, Ihao Chen +6 more | 2006-07-18 |
| 7080234 | VLIW computer processing architecture having the problem counter stored in a register file register | Nyles Nettleton, Michael Parkin, David R. Emberson | 2006-07-18 |
| 7043596 | Method and apparatus for simulation processor | Thomas M. McWilliams, Jeffrey B. Rubin, Michael Parkin, Oyekunle A. Olukotun, Derek Pappas +7 more | 2006-05-09 |
| 7028170 | Processing architecture having a compare capability | — | 2006-04-11 |
| 7020763 | Computer processing architecture having a scalable number of processing paths and pipelines | Michael Parkin, Daniel S. Rice | 2006-03-28 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations | — | 2006-03-14 |
| 6988181 | VLIW computer processing architecture having a scalable number of register files | Michael Parkin, Daniel S. Rice | 2006-01-17 |
| 6892295 | Processing architecture having an array bounds check capability | — | 2005-05-10 |
| 6859904 | Apparatus and method to facilitate self-correcting memory | James E. Kocol, Sandra Lee | 2005-02-22 |
| 6816961 | Processing architecture having field swapping capability | Daniel S. Rice | 2004-11-09 |
| 6779087 | Method and apparatus for checkpointing to facilitate reliable execution | James E. Kocol, Sandra Lee | 2004-08-17 |
| 6766428 | Method and apparatus for storing prior versions of modified values to facilitate reliable execution | James E. Kocol, Sandra Lee | 2004-07-20 |
| 6732143 | Method and system for integrating telephone voice communications into a client-server architecture | — | 2004-05-04 |
| 6631439 | VLIW computer processing architecture with on-chip dynamic RAM | Nyles Nettleton, Michael Parkin | 2003-10-07 |
| 6314510 | Microprocessor with reduced context switching overhead and corresponding method | Daniel S. Rice | 2001-11-06 |
| 6199142 | Processor/memory device with integrated CPU, main memory, and full width cache and associated method | Andreas Nowatzyk, Fong Pong | 2001-03-06 |
| 6128702 | Integrated processor/memory device with victim data cache | Andreas Nowatzyk, Fong Pong | 2000-10-03 |