Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9703565 | Combined branch target and predicate prediction | Douglas C. Burger | 2017-07-11 |
| 9571399 | Method and apparatus for congestion-aware routing in a computer interconnection network | Paul Gratz, Boris Grot | 2017-02-14 |
| 9477526 | Cache utilization and eviction based on allocated priority tokens | Daniel R. Johnson, Minsoo Rhu, James M. O'Connor | 2016-10-25 |
| 9058453 | System and method for configuring a channel | William J. Dally, Steven L. Scott, Brucek Kurdo Khailany, Michael Allen Parker | 2015-06-16 |
| 9021241 | Combined branch target and predicate prediction for instruction blocks | Douglas C. Burger | 2015-04-28 |
| 8732711 | Two-level scheduler for multi-threaded processing | William J. Dally, David Tarjan, John Erik Lindholm, Mark Alan Gebhart, Daniel R. Johnson | 2014-05-20 |
| 8447911 | Unordered load/store queue | Douglas C. Burger, Robert Gregory McDonald, Lakshminarasimhan Sethumadhavan, Franziska Roesner | 2013-05-21 |
| 8433885 | Method, system and computer-accessible medium for providing a distributed predicate prediction | Doug Burger, Hadi Esmaeilzadeh | 2013-04-30 |
| 8307116 | Scalable bus-based on-chip interconnection networks | Boris Grot | 2012-11-06 |
| 8285900 | Method and apparatus for congestion-aware routing in a computer interconnection network | Paul Gratz, Boris Grot | 2012-10-09 |
| 8180997 | Dynamically composing processor cores to form logical processors | Douglas C. Burger, Robert Gregory McDonald, Paul Gratz, Nitya Ranganathan, Lakshminarasimhan Sethumadhavan +4 more | 2012-05-15 |
| 8127119 | Control-flow prediction using multiple independent predictors | Doug Burger, Nitya Ranganathan | 2012-02-28 |
| 8055881 | Computing nodes for executing groups of instructions | Douglas C. Burger, Karthikevan Sankaralingam, Ramadass Nagarajan | 2011-11-08 |
| 6965969 | Non-uniform cache apparatus, systems, and methods | Doug Burger, Changkyu Kim | 2005-11-15 |
| 6003123 | Memory system with global address translation | Nicholas P. Carter, William J. Dally | 1999-12-14 |
| 5845331 | Memory system including guarded pointers | Nicholas P. Carter, William J. Dally | 1998-12-01 |
| 5574939 | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism | William J. Dally | 1996-11-12 |