Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9830158 | Speculative execution and rollback | Jack Choquette, Robert J. Stoll, Xiaogang Qiu | 2017-11-28 |
| 9798548 | Methods and apparatus for scheduling instructions using pre-decode data | Jack Choquette, Robert J. Stoll | 2017-10-24 |
| 9798544 | Reordering buffer for memory access locality | Jack Choquette, Xiaogang Qiu, Robert J. Stoll | 2017-10-24 |
| 9612836 | System, method, and computer program product for implementing software-based scoreboarding | Robert Ohannessian, Michael A. Fetterman, Jack Choquette, Xiaogang Qiu, Shirish Gadre +1 more | 2017-04-04 |
| 9606808 | Method and system for resolving thread divergences | Jack Choquette, Xiaogang Qiu, Jeff Tuckey, Michael Siu, Robert J. Stoll | 2017-03-28 |
| 9477480 | System and processor for implementing interruptible batches of instructions | Robert Ohannessian, Jack Choquette, Michael A. Fetterman | 2016-10-25 |
| 9471307 | System and processor that include an implementation of decoupled pipelines | Michael A. Fetterman, Robert Ohannessian, Shirish Gadre, Jack Choquette, Xiaogang Qiu +2 more | 2016-10-18 |
| 9459876 | System, method, and computer program product for managing divergences and synchronization points during thread block execution by using a double sided queue for token storage | Gregory Diamos | 2016-10-04 |
| 9430242 | Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT | Peter Nelson, Jack Choquette | 2016-08-30 |
| 9405561 | Method and system for memory overlays for portable function pointers | — | 2016-08-02 |
| 8949841 | Approach for a configurable phase-based priority scheduler | Jack Choquette, Robert J. Stoll, Gary M. Tarolli, John Erik Lindholm | 2015-02-03 |
| 8930636 | Relaxed coherency between different caches | Joel J. McCormack, Rajesh Kota, Emmett M. Kilgariff | 2015-01-06 |