Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9424045 | Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit | Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon, Frederic Claude Marie Piry, Albin Pierick Tonnerre | 2016-08-23 |
| 9400655 | Technique for freeing renamed registers | Guillaume Schon, Frederic Jean Denis Arsanto, Luca Scalabrino | 2016-07-26 |
| 9361111 | Tracking speculative execution of instructions for a register renaming data store | Luca Scalabrino, Melanie Emanuelle Lucie Teyssier, Guillaume Schon | 2016-06-07 |
| 9311087 | Sticky bit update within a speculative execution processing environment | Luca Scalabrino, Guillaume Schon, Frederic Jean Denis Arsanto | 2016-04-12 |
| 9286069 | Dynamic write port re-arbitration | Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon | 2016-03-15 |
| 9280675 | Encrypting and storing confidential data | Jean-Baptiste Brelot | 2016-03-08 |
| 9201656 | Data processing apparatus and method for performing register renaming for certain data processing operations without additional registers | Jean-Baptiste Brelot | 2015-12-01 |
| 9170819 | Forwarding condition information from first processing circuitry to second processing circuitry | Nicolas Chaussade, Luca Scalabrino, Frederic Jean Denis Arsanto | 2015-10-27 |
| 8352794 | Control of clock gating | Rémi Marius Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert | 2013-01-08 |
| 7984269 | Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction | Luc Orion, Boris S. Alvarez-Heredia | 2011-07-19 |
| 7925868 | Suppressing register renaming for conditional instructions predicted as not executed | Norbert Bernard Eugene Lataille, Florent Begon, Melanie Emanuelle Lucie Vincent | 2011-04-12 |
| 7856532 | Cache logic, data processing apparatus including cache logic, and a method of operating cache logic | Norbert Bernard Eugene Lataille, Philippe Jean-Pierre Raphalen | 2010-12-21 |
| 7844800 | Method for renaming a large number of registers in a data processing system using a background channel | Melanie Emanuelle Lucie Vincent, Florent Begon, Norbert Bernard Eugene Lataille | 2010-11-30 |
| 7698537 | Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming | Melanie Emanuelle Lucie Vincent, Luc Orion, Norbert Bernard Eugene Lataille | 2010-04-13 |
| 7624253 | Determining register availability for register renaming | Florent Begon, Norbert Bernard Eugene Lataille, Melanie Emanuelle Lucie Vincent | 2009-11-24 |
| 7472225 | Caching data | Rahoul Kumar Varma, David Francis McHale, Philippe Jean-Pierre Raphalen, Christophe Justin Evrard | 2008-12-30 |
| 7434007 | Management of cache memories in a data processing apparatus | Christophe Evrard, Philippe Jean-Pierre Raphalen | 2008-10-07 |
| 7152186 | Cross-triggering of processing devices | Nicholas E. Smith, Paul Kimelman, Ian Field, Man Cheung Joseph Yiu, David Francis McHale +1 more | 2006-12-19 |