Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8136098 | Using pushdown systems for the static analysis of multi-threaded programs | Vineet Kahlon | 2012-03-13 |
| 8131532 | Software verification using range analysis | Srihari Cadambi, Aleksandr Zaks, Franjo Ivancic, Ilya SHLYAKHTER, Zijiang Yang +2 more | 2012-03-06 |
| 8126831 | System and method for dynamically inferring data preconditions over predicates by tree learning | Sriram Sankaranarayanan, Franjo Ivancic | 2012-02-28 |
| 8005661 | Modeling and verification of concurrent systems using SMT-based BMC | Malay Ganai | 2011-08-23 |
| 8006239 | Program analysis using symbolic ranges | Sriram Sankaranarayanan, Franjo Ivancic, Ilya SHLYAKHTER | 2011-08-23 |
| 7930659 | Software verification | Franjo Ivancic, Malay Ganai, Himanshu Jain | 2011-04-19 |
| 7926039 | Reachability analysis for program verification | Chao Wang, Zijiang Yang | 2011-04-12 |
| 7853906 | Accelerating high-level bounded model checking | Malay Ganai | 2010-12-14 |
| 7784035 | Method for the static analysis of concurrent multi-threaded software | Vineet Kahlon | 2010-08-24 |
| 7742907 | Iterative abstraction using SAT-based BMC with proof analysis | Malay Ganai, Zijiang Yang, Pranav Ashar | 2010-06-22 |
| 7743352 | Computer implemented method of high-level synthesis for the efficient verification of computer software | Malay Ganai | 2010-06-22 |
| 7711525 | Efficient approaches for bounded model checking | Malay Ganai, Lintao Zhang, Zijiang Yang, Pranav Ashar | 2010-05-04 |
| 7693690 | Disjunctive image computation for sequential systems | Chao Wang, Zijiang Yang, Franjo Ivancic | 2010-04-06 |
| 7386818 | Efficient modeling of embedded memories in bounded memory checking | Malay Ganai, Pranav Ashar | 2008-06-10 |
| 7346486 | System and method for modeling, abstraction, and analysis of software | Franjo Ivancic, Pranav Ashar, Malay Ganai, Zijiang Yang | 2008-03-18 |
| 7305637 | Efficient SAT-based unbounded symbolic model checking | Malay Ganai, Pranav Ashar | 2007-12-04 |
| 7203917 | Efficient distributed SAT and SAT-based distributed bounded model checking | Malay Ganai, Zijiang Yang, Pranav Ashar | 2007-04-10 |
| 6975976 | Property specific testbench generation framework for circuit design validation by guided simulation | Albert E. Casavant, Pranav Ashar | 2005-12-13 |
| 6874135 | Method for design validation using retiming | Pranav Ashar, Sharad Malik | 2005-03-29 |
| 6745160 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Pranav Ashar, Anand Raghunathan, Subhrajit Bhattacharya | 2004-06-01 |
| 6728665 | SAT-based image computation with application in reachability analysis | Zijiang Yang, Pranav Ashar | 2004-04-27 |
| 6662323 | Fast error diagnosis for combinational verification | Pranav Ashar | 2003-12-09 |
| 6651234 | Partition-based decision heuristics for SAT and image computation using SAT and BDDs | Zijiang Yang, Pranav Ashar, Sharad Malik | 2003-11-18 |
| 6496961 | Dynamic detection and removal of inactive clauses in SAT with application in image computation | Zijiang Yang, Anubhav Gupta, Pranav Ashar | 2002-12-17 |
| 6035109 | Method for using complete-1-distinguishability for FSM equivalence checking | Pranav Ashar, Sharad Malik | 2000-03-07 |