Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6689640 | Chip scale pin array | — | 2004-02-10 |
| 6683368 | Lead frame design for chip scale package | — | 2004-01-27 |
| 6589814 | Lead frame chip scale package | Joseph O. Smith | 2003-07-08 |
| 6468832 | Method to encapsulate bumped integrated circuit to create chip scale package | — | 2002-10-22 |
| 6420212 | Method and apparatus to enclose dice | — | 2002-07-16 |
| 6352878 | Method for molding a bumped wafer | Joseph O. Smith | 2002-03-05 |
| 6245595 | Techniques for wafer level molding of underfill encapsulant | Luu Thanh Nguyen, Hem Takiar, Ethan Warner, Joseph O. Smith | 2001-06-12 |
| 6184575 | Ultra-thin composite package for integrated circuits | Satya Chillara | 2001-02-06 |
| 6130473 | Lead frame chip scale package | Joseph O. Smith | 2000-10-10 |
| 6117710 | Plastic package with exposed die and method of making same | Joseph O. Smith | 2000-09-12 |
| 6054772 | Chip sized package | Joseph O. Smith | 2000-04-25 |
| 6034423 | Lead frame design for increased chip pinout | Joseph O. Smith | 2000-03-07 |
| 5986340 | Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same | Joseph O. Smith | 1999-11-16 |
| 5894108 | Plastic package with exposed die | Joseph O. Smith | 1999-04-13 |
| 5783870 | Method for connecting packages of a stacked ball grid array structure | Joseph O. Smith | 1998-07-21 |
| 5739581 | High density integrated circuit package assembly with a heatsink between stacked dies | Satya Chillara | 1998-04-14 |
| 5705851 | Thermal ball lead integrated package | Satya Chillara, Jagdish G. Belani | 1998-01-06 |
| 5663593 | Ball grid array package with lead frame | Joseph O. Smith | 1997-09-02 |
| 5650659 | Semiconductor component package assembly including an integral RF/EMI shield | Satya Chillara, Jagdish G. Belani | 1997-07-22 |
| 5648679 | Tape ball lead integrated circuit package | Satya Chillara | 1997-07-15 |
| 5598321 | Ball grid array with heat sink | Joseph O. Smith | 1997-01-28 |
| 5569955 | High density integrated circuit assembly combining leadframe leads with conductive traces | Satya Chillara | 1996-10-29 |
| 5498901 | Lead frame having layered conductive planes | Satya Chillara | 1996-03-12 |
| 5442230 | High density integrated circuit assembly combining leadframe leads with conductive traces | Satya Chillara | 1995-08-15 |
| 5408127 | Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components | — | 1995-04-18 |