Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7563686 | Method for forming a memory device with a recessed gate | Pei-Ing Lee, Chien-Li Cheng | 2009-07-21 |
| 7557012 | Method for forming surface strap | Chih-Hao Cheng, Tzung-Han Lee | 2009-07-07 |
| 7535045 | Checkerboard deep trench dynamic random access memory cell array layout | Chien-Li Cheng, Chin-Tien Yang, Tzung-Han Lee, Shian-Hau Liao | 2009-05-19 |
| 7446355 | Electrical device and method for fabricating the same | Shian-Jyh Lin, Chien-Li Cheng, Pei-Ing Lee | 2008-11-04 |
| 7316978 | Method for forming recesses | Pei-Ing Lee, Chien-Li Cheng | 2008-01-08 |
| 7205075 | Method of forming a vertical memory device with a rectangular trench | Yu-Sheng Shu, Yuan-Hsun Wu, Shian-Jyh Lin | 2007-04-17 |
| 7179748 | Method for forming recesses | Pei-Ing Lee, Chien-Li Cheng | 2007-02-20 |
| 7030431 | Metal gate with composite film stack | Shian-Jyh Lin, Yu-Chang Lin | 2006-04-18 |
| 6992021 | Method for forming a silicon nitride layer | Shian-Jyh Lin, Hai-Han Hung | 2006-01-31 |
| 6977227 | Method of etching bottle trench and fabricating capacitor with same | Shian-Jyh Lin, Yu-Sheng Hsu | 2005-12-20 |
| 6958283 | Method for fabricating trench isolation | Chien-Mao Liao, Tzu-En Ho, Chang-Rong Wu, Chih-How Chang, Sheng-Wei Yang +3 more | 2005-10-25 |
| 6818547 | Dual damascene process | Meng-Hung Chen, Yu-Sheng Shu, Ming-Hung Lo | 2004-11-16 |
| 6767786 | Method for forming bottle trenches by liquid phase oxide deposition | Shian-Jyh Lin, Meng-Hung Chen | 2004-07-27 |
| 6576530 | Method of fabricating shallow trench isolation | Yi-Nan Chen, Chung-Peng Hao | 2003-06-10 |
| 6403483 | Shallow trench isolation having an etching stop layer and method for fabricating same | Chung-Peng Hao, Chung-Lin Huang, Yih-Ren Shao, Pei-Ing Lee | 2002-06-11 |
| 6046079 | Method for prevention of latch-up of CMOS devices | Joe Ko | 2000-04-04 |
| 5998832 | Metal oxide semiconductor device for an electro-static discharge circuit | Shing-Ren Sheu | 1999-12-07 |
| 5985709 | Process for fabricating a triple-well structure for semiconductor integrated circuit devices | Chun-Yen Chang, Sun-Chieh Chien, Chen-Chiu Hsu | 1999-11-16 |
| 5858826 | Method of making a blanket N-well structure for SRAM data stability in P-type substrates | Chun-Yen Chang, Sun-Chieh Chien, Chen-Chiu Hsue | 1999-01-12 |
| 5698458 | Multiple well device and process of manufacture | Chen-Chiu Hsue, Sun-Chieh Chien, Ming-Tzong Yang | 1997-12-16 |
| 5576557 | Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits | Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Joe Ko | 1996-11-19 |
| 5571737 | Metal oxide semiconductor device integral with an electro-static discharge circuit | Shing-Ren Sheu | 1996-11-05 |
| 5541801 | Low-voltage gate trigger SCR (LVGTSCR) ESD protection circuit for input and output pads | Chun-Yen Chang | 1996-07-30 |
| 5473169 | Complementary-SCR electrostatic discharge protection circuit | Ming-Dou Ker, Chung-Yu Wu, Joe Ko | 1995-12-05 |
| 5289334 | CMOS on-chip ESD protection circuit and semiconductor structure | Ming-Dou Ker, Chung-Yu Wu | 1994-02-22 |