Issued Patents All Time
Showing 126–146 of 146 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5815454 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1998-09-29 |
| 5805519 | Semiconductor memory device | — | 1998-09-08 |
| 5774405 | Dynamic random access memory having an internal circuit using a boosted potential | — | 1998-06-30 |
| 5724293 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1998-03-03 |
| 5696727 | Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption | Masaki Tsukude, Kazutami Arimoto | 1997-12-09 |
| 5687123 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto +1 more | 1997-11-11 |
| 5682343 | Hierarchical bit line arrangement in a semiconductor memory | Masaki Tsukude, Mikio Asakura, Kazuyasu Fujishima | 1997-10-28 |
| 5650972 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1997-07-22 |
| 5619164 | Pseudo ground line voltage regulator | — | 1997-04-08 |
| 5617369 | Dynamic semiconductor memory device having excellent charge retention characteristics | Kazutami Arimoto | 1997-04-01 |
| 5612920 | Semiconductor memory device having a voltage down converter for generating an internal power supply voltage from an external power supply | — | 1997-03-18 |
| 5604707 | Semiconductor memory device responsive to hierarchical internal potentials | Shigehiro Kuge, Kazutami Arimoto, Hideto Hidaka, Takahiro Tsuruda | 1997-02-18 |
| 5604710 | Arrangement of power supply and data input/output pads in semiconductor memory device | Mikio Asakura, Masaki Tsukude, Kazutami Arimoto | 1997-02-18 |
| 5602793 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1997-02-11 |
| 5574397 | Signal output circuit operating stably and arrangement of power supply interconnection line therefor in semiconductor integrated circuit device | Hideto Hidaka, Masakazu Hirose, Takahiro Tsuruda | 1996-11-12 |
| 5513142 | Semiconductor memory device for maintaining level of signal line | Kazutami Arimoto, Hideto Hidaka | 1996-04-30 |
| 5426615 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1995-06-20 |
| 5390140 | Signal output circuit operating stably and arrangement of power supply interconnection line therefor in semiconductor integrated circuit device | Hideto Hidaka, Masakazu Hirose, Takahiro Tsuruda | 1995-02-14 |
| 5325336 | Semiconductor memory device having power line arranged in a meshed shape | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka | 1994-06-28 |
| 5321646 | Layout of a semiconductor memory device | Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi | 1994-06-14 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1994-05-24 |