Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5355012 | Semiconductor device | Yasuo Yamaguchi, Tsuyoshi Yamano | 1994-10-11 |
| 5347151 | DRAM with memory cells having access transistor formed on solid phase epitaxial single crystalline layer and manufacturing method thereof | Masahiro Shimizu, Takehisa Yamaguchi | 1994-09-13 |
| 5341028 | Semiconductor device and a method of manufacturing thereof | Yasuo Yamaguchi, Tsuyoshi Yamano | 1994-08-23 |
| 5338957 | Nonvolatile semiconductor device and a method of manufacturing thereof | Atsushi Fukumoto, Makoto Ohi, Hiroshi Onoda, Yuichi Kunori | 1994-08-16 |
| 5338699 | Method of making a semiconductor integrated device having gate sidewall structure | Makoto Ohi, Hideaki Arima, Atsushi Hachisuka, Yasushi Matsui | 1994-08-16 |
| 5275629 | Semiconductor device manufacturing apparatus | Masahiro Shimizu, Takehisa Yamaguchi | 1994-01-04 |
| 5276344 | Field effect transistor having impurity regions of different depths and manufacturing method thereof | Hideaki Arima, Makoto Ohi, Atsushi Hachisuka, Tomonori Okudaira | 1994-01-04 |
| 5240872 | Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions | Kaoru Motonami, Atsushi Hachisuka, Yoshinori Okumura, Yasushi Matsui | 1993-08-31 |
| 5233212 | Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension | Makoto Ohi, Hideaki Arima, Atsushi Hachisuka, Yasushi Matsui | 1993-08-03 |
| 5218219 | Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region | Hideaki Arima, Kaoru Motonami, Atsushi Hachisuka, Tomonori Okudaira | 1993-06-08 |
| 5194925 | Electrically programmable non-volatie semiconductor memory device | Hideaki Arima | 1993-03-16 |
| 5173752 | Semiconductor device having interconnection layer contacting source/drain regions | Kaoru Motonami, Atsushi Hachisuka, Yoshinori Okumura, Yasushi Matsui | 1992-12-22 |
| 5162262 | Multi-layered interconnection structure for a semiconductor device and manufactured method thereof | Hideaki Arima | 1992-11-10 |
| 5141891 | MIS-type semiconductor device of LDD structure and manufacturing method thereof | Hideaki Arima | 1992-08-25 |
| 5100818 | Non-volatile semiconductor memory device and method of manufacturing the same | Hideaki Arima | 1992-03-31 |
| 5093277 | Method of device isolation using polysilicon pad LOCOS method | Hideaki Arima | 1992-03-03 |
| 5051948 | Content addressable memory device | Kiyoto Watabe, Hirofumi Shinohara, Takahisa Eimori, Hideaki Arima, Yuichi Nakashima +1 more | 1991-09-24 |
| 5049975 | Multi-layered interconnection structure for a semiconductor device | Hideaki Arima | 1991-09-17 |
| 4988635 | Method of manufacturing non-volatile semiconductor memory device | Hideaki Arima | 1991-01-29 |
| 4989054 | Non-volatile semiconductor memory device using contact hole connection | Hideaki Arima | 1991-01-29 |