MI

Masayuki Iketani

Mitsubishi Electric: 9 patents #3,275 of 25,717Top 15%
HI Hitachi: 2 patents #13,388 of 28,497Top 50%
HE Hitachi Vlsi Engineering: 2 patents #292 of 666Top 45%
RT Renesas Technology: 1 patents #1,991 of 3,337Top 60%
Overall (All Time): #427,072 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
6813202 Semiconductor integrated circuit device capable of shortening period required for performing data retention test 2004-11-02
6229365 Semiconductor integrated circuit device operating stably at a plurality of power supply voltage levels Shigeki Ohbayashi 2001-05-08
5764573 Semiconductor device capable of externally and readily identifying set bonding optional function and method of identifying internal function of semiconductor device Shigeki Ohbayashi 1998-06-09
5703510 Power on reset circuit for generating reset signal at power on Shigeki Ohbayashi 1997-12-30
5659513 Static semiconductor memory device having improved characteristics Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1997-08-19
5629900 Semiconductor memory device operable to write data accurately at high speed Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1997-05-13
5544105 Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1996-08-06
5515326 Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1996-05-07
5506805 Static semiconductor memory device having circuitry for enlarging write recovery margin Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1996-04-09
5491655 Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode Toshihiko Hirose, Shigeki Ohbayashi, Setsu Kondo, Takashi Hayasaka, Yoshiyuki Fujino 1996-02-13
5188280 Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Kunizo Sahara, Ikuo Yoshida +6 more 1993-02-23
5090609 Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Kunizo Sahara, Ikuo Yoshida +6 more 1992-02-25