Issued Patents All Time
Showing 276–300 of 320 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5870347 | Multi-bank memory input/output line selection | Brent Keeth | 1999-02-09 |
| 5859442 | Circuit and method for configuring a redundant bond pad for probing a semiconductor | — | 1999-01-12 |
| 5852371 | Low power, high speed level shifter | Todd A. Merritt | 1998-12-22 |
| 5850368 | Burst EDO memory address counter | Adrian E. Ong, Paul S. Zagar, Brett Williams | 1998-12-15 |
| 5835440 | Memory device equilibration circuit and method | — | 1998-11-10 |
| 5831895 | Dynamic cell plate sensing and equilibration in a memory device | — | 1998-11-03 |
| 5831931 | Address strobe recognition in a memory device | — | 1998-11-03 |
| 5831929 | Memory device with staggered data paths | — | 1998-11-03 |
| 5825711 | Method and system for storing and processing multiple memory addresses | — | 1998-10-20 |
| 5818780 | Memory device with distributed voltage regulation system | — | 1998-10-06 |
| 5812488 | Synchronous burst extended data out dram | Paul S. Zagar, Todd A. Merritt | 1998-09-22 |
| 5802010 | Burst EDO memory device | Paul S. Zagar, Brett Williams | 1998-09-01 |
| 5793692 | Integrated circuit memory with back end mode disable | Todd A. Merritt | 1998-08-11 |
| 5781490 | Multiple staged power up of integrated circuit | Manny K. F. Ma | 1998-07-14 |
| 5757705 | SDRAM clocking test mode | — | 1998-05-26 |
| 5757703 | Distributed write data drivers for burst access memories | Todd A. Merritt | 1998-05-26 |
| 5751031 | Memory and other integrated circuitry having a conductive interconnect line pitch of less than 0.6 micron | J. Wayne Thompson | 1998-05-12 |
| 5745429 | Memory having and method for providing a reduced access time | Timothy B. Cowles, Todd A. Merritt | 1998-04-28 |
| 5729503 | Address transition detection on a synchronous design | — | 1998-03-17 |
| 5724288 | Data communication for memory | Eugene H. Cloud, Brett Williams | 1998-03-03 |
| 5721859 | Counter control circuit in a burst memory | — | 1998-02-24 |
| 5717654 | Burst EDO memory device with maximized write cycle timing | — | 1998-02-10 |
| 5710740 | Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM | — | 1998-01-20 |
| 5703813 | DRAM having multiple column address strobe operation | Todd A. Merritt, Brett Williams | 1997-12-30 |
| 5684751 | Dynamic memory refresh controller utilizing array voltage | — | 1997-11-04 |