Issued Patents All Time
Showing 226–250 of 320 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6175905 | Method and system for bypassing pipelines in a pipelined memory command generator | — | 2001-01-16 |
| 6169331 | Apparatus for electrically coupling bond pads of a microelectronic device | Michael B. Ball | 2001-01-02 |
| 6167495 | Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories | Brent Keeth | 2000-12-26 |
| 6137312 | Voltage level translator | — | 2000-10-24 |
| 6122217 | Multi-bank memory input/output line selection | Brent Keeth | 2000-09-19 |
| 6108251 | Method and apparatus for remapping memory addresses for redundancy | — | 2000-08-22 |
| 6107111 | Circuit and method for configuring a redundant bond pad for probing a semiconductor | — | 2000-08-22 |
| 6105106 | Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times | — | 2000-08-15 |
| 6101197 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges | Brent Keeth | 2000-08-08 |
| 6094727 | Method and apparatus for controlling the data rate of a clocking circuit | — | 2000-07-25 |
| 6094704 | Memory device with pipelined address path | Chris G. Martin | 2000-07-25 |
| 6075741 | Multiple staged power up of integrated circuit | Manny K. F. Ma | 2000-06-13 |
| 6069832 | Method for multiple staged power up of integrated circuit | Manny K. F. Ma | 2000-05-30 |
| 6064600 | Methods and apparatus for reading memory device register data | — | 2000-05-16 |
| 6057725 | Protection circuit for use during burn-in testing | — | 2000-05-02 |
| 6055193 | Charge pump circuits and devices containing such | Manny K. F. Ma | 2000-04-25 |
| 6043558 | IC packages including separated signal and power supply edge connections, systems and devices including such packages, and methods of connecting such packages | — | 2000-03-28 |
| 6032274 | Method and apparatus for compressed data testing of more than one memory array | — | 2000-02-29 |
| 6032220 | Memory device with dual timing and signal latching control | Chris G. Martin | 2000-02-29 |
| 6029252 | Method and apparatus for generating multi-phase clock signals, and circuitry, memory devices, and computer systems using same | — | 2000-02-22 |
| 6026050 | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same | Russel J. Baker | 2000-02-15 |
| 6014759 | Method and apparatus for transferring test data from a memory array | — | 2000-01-11 |
| 6009501 | Method and apparatus for local control signal generation in a memory device | — | 1999-12-28 |
| 6009034 | Memory device with distributed voltage regulation system | — | 1999-12-28 |
| 6005823 | Memory device with pipelined column address path | Chris G. Martin, Brent Keeth | 1999-12-21 |