Issued Patents All Time
Showing 301–320 of 320 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5682354 | CAS recognition in burst extended data out DRAM | — | 1997-10-28 |
| 5675549 | Burst EDO memory device address counter | Adrian E. Ong, Paul S. Zagar, Brett L. Wiliams | 1997-10-07 |
| 5668773 | Synchronous burst extended data out DRAM | Paul S. Zagar, Todd A. Merritt | 1997-09-16 |
| 5666070 | Low power, high speed level shifter | Todd A. Merritt | 1997-09-09 |
| 5657293 | Integrated circuit memory with back end mode disable | Todd A. Merritt | 1997-08-12 |
| 5652724 | Burst EDO memory device having pipelined output buffer | — | 1997-07-29 |
| 5646898 | Two stage driver circuit | — | 1997-07-08 |
| 5642073 | System powered with inter-coupled charge pumps | — | 1997-06-24 |
| 5610864 | Burst EDO memory device with maximized write cycle timing | — | 1997-03-11 |
| 5604714 | DRAM having multiple column address strobe operation | Todd A. Merritt, Brett Williams | 1997-02-18 |
| 5598376 | Distributed write data drivers for burst access memories | Todd A. Merritt | 1997-01-28 |
| 5596534 | Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM | — | 1997-01-21 |
| 5587671 | Semiconductor device having an output buffer which reduces signal degradation due to leakage of current | Paul S. Zagar | 1996-12-24 |
| 5574697 | Memory device with distributed voltage regulation system | — | 1996-11-12 |
| 5539703 | Dynamic memory device including apparatus for controlling refresh cycle time | — | 1996-07-23 |
| 5528173 | Low power, high speed level shifter | Todd A. Merritt | 1996-06-18 |
| 5526320 | Burst EDO memory device | Paul S. Zagar, Brett Williams | 1996-06-11 |
| 5493249 | System powered with inter-coupled charge pumps | — | 1996-02-20 |
| 5392251 | Controlling dynamic memory refresh cycle time | — | 1995-02-21 |
| 5335202 | Verifying dynamic memory refresh | William R Bachand | 1994-08-02 |