Issued Patents All Time
Showing 126–150 of 282 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7824994 | Method of forming memory devices by performing halogen ion implantation and diffusion processes | Kirk D. Prall, Behnam Moradi, Di Li, Chris Larsen | 2010-11-02 |
| 7800947 | Multiple select gates with non-volatile memory cells | — | 2010-09-21 |
| 7795664 | Finned memory cells | — | 2010-09-14 |
| 7787277 | Semiconductor memory device capable of realizing a chip with high operation reliability and high yield | Hiroshi Nakamura, Ken Takeuchi, Hideko Oodaira, Kenichi Imamiya, Kazuhito Narita +1 more | 2010-08-31 |
| 7773418 | Non-volatile memory with both single and multiple level cells | — | 2010-08-10 |
| 7768839 | Memory read methods, apparatus, and systems | — | 2010-08-03 |
| 7768838 | Operating memory cells | — | 2010-08-03 |
| 7763933 | Transistor constructions and processing methods | — | 2010-07-27 |
| 7755940 | Method, apparatus, and system for erasing memory | — | 2010-07-13 |
| 7749836 | Nonvolatile semiconductor memory and manufacturing method thereof | — | 2010-07-06 |
| 7751236 | MEM suspended gate non-volatile memory | — | 2010-07-06 |
| 7742335 | Non-volatile multilevel memory cells | — | 2010-06-22 |
| 7738291 | Memory page boosting method, device and system | Jeffrey C. Antosh, Roderick C. Frianeza | 2010-06-15 |
| 7733705 | Reduction of punch-through disturb during programming of a memory device | Alessandro Torsi, Carlo Musilli | 2010-06-08 |
| 7729171 | Multiple select gate architecture with select gates of different lengths | — | 2010-06-01 |
| 7724577 | NAND with back biased operation | Akira Goda | 2010-05-25 |
| 7715239 | Memory voltage cycle adjustment | — | 2010-05-11 |
| 7715234 | Reducing effects of program disturb in a memory device | Todd A. Marquart | 2010-05-11 |
| 7701765 | Non-volatile multilevel memory cell programming | — | 2010-04-20 |
| 7697335 | Multiple select gate architecture | — | 2010-04-13 |
| 7684243 | Reducing read failure in a memory device | Alessandro Torsi, Carlo Musilli | 2010-03-23 |
| 7675778 | Memory devices having reduced word line current and method of operating and manufacturing the same | — | 2010-03-09 |
| 7675772 | Multilevel memory cell operation | Akira Goda | 2010-03-09 |
| 7668012 | Memory cell programming | — | 2010-02-23 |
| 7663930 | Programming a non-volatile memory device | — | 2010-02-16 |