Issued Patents All Time
Showing 76–100 of 282 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8228742 | Memory read methods, apparatus, and systems | — | 2012-07-24 |
| 8223549 | NAND flash memory programming | Haitao Liu, Di Li | 2012-07-17 |
| 8208278 | Couplings within memory devices | Akira Goda | 2012-06-26 |
| 8199572 | Non-volatile memory with both single and multiple level cells | — | 2012-06-12 |
| 8193590 | Interconnecting bit lines in memory devices for multiplexing | — | 2012-06-05 |
| 8164950 | Reduction of punch-through disturb during programming of a memory device | Alessandro Torsi, Carlo Musilli | 2012-04-24 |
| 8163610 | Fabrication of finned memory arrays | — | 2012-04-24 |
| 8159879 | Reducing effects of program disturb in a memory device | — | 2012-04-17 |
| 8154926 | Memory cell programming | — | 2012-04-10 |
| 8144519 | Programming a flash memory device | — | 2012-03-27 |
| 8129781 | Method of forming memory devices by performing halogen ion implantation and diffusion processes | Kirk D. Prall, Behnam Moradi, Di Li, Chris Larsen | 2012-03-06 |
| 8120954 | Method, apparatus, and system for erasing memory | — | 2012-02-21 |
| 8116135 | Non-volatile memory cell read failure reduction | — | 2012-02-14 |
| 8116137 | Memory cell operation | Akira Goda | 2012-02-14 |
| 8102707 | Non-volatile multilevel memory cells | — | 2012-01-24 |
| 8084802 | Nonvolatile semiconductor memory | Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Toshitake Yaegashi, Yuji Takeuchi +3 more | 2011-12-27 |
| 8072814 | NAND with back biased operation | Akira Goda | 2011-12-06 |
| 8069382 | Memory cell programming | — | 2011-11-29 |
| 8059474 | Reducing read failure in a memory device | Alessandro Torsi, Carlo Musilli | 2011-11-15 |
| 8050090 | Memory page boosting method, device and system | Jeffrey C. Antosh, Roderick C. Frianeza | 2011-11-01 |
| 8050096 | Programming method to reduce gate coupling interference for non-volatile memory | — | 2011-11-01 |
| 8030211 | Methods for forming bit line contacts and bit lines during the formation of a semiconductor device | — | 2011-10-04 |
| 8023329 | Reducing effects of program disturb in a memory device | Todd A. Marquart | 2011-09-20 |
| 8018778 | Memory read methods, apparatus, and systems | — | 2011-09-13 |
| 8004031 | Memory device transistors | — | 2011-08-23 |