Issued Patents All Time
Showing 51–75 of 168 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11586566 | Memory protocol with command priority | — | 2023-02-21 |
| 11580039 | Channel depth adjustment in memory systems | — | 2023-02-14 |
| 11567700 | Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue | Patrick A. La Fratta | 2023-01-31 |
| 11550725 | Dynamically sized redundant write buffer with sector-based tracking | Cagdas Dirik | 2023-01-10 |
| 11543978 | Credit-based scheduling of memory commands | Patrick A. La Fratta | 2023-01-03 |
| 11526306 | Command scheduling in a memory subsystem according to a selected scheduling ordering | Patrick A. La Fratta | 2022-12-13 |
| 11507504 | Memory sub-system for decoding non-power-of-two addressable unit address boundaries | Patrick A. La Fratta, Chandrasekhar Nagarajan | 2022-11-22 |
| 11494119 | Memory searching component | Elliott C. Cooper-Balis, Paul Rosenfeld | 2022-11-08 |
| 11442648 | Data migration dynamic random access memory | Paul Rosenfeld, Patrick A. La Fratta | 2022-09-13 |
| 11422705 | Non-deterministic memory protocol | James A. Hall, Jr., Frank F. Ross | 2022-08-23 |
| 11403035 | Memory module including a controller and interfaces for communicating with a host and another memory module | — | 2022-08-02 |
| 11403240 | Memory having internal processors and data communication methods in memory | Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski | 2022-08-02 |
| 11397683 | Low latency cache for non-volatile memory in a hybrid DIMM | Horia Simionescu, Paul Stonelake, Chung Kuang Chin, Narasimhulu Dharanikumar Kotte, Cagdas Dirik | 2022-07-26 |
| 11372763 | Prefetch for data interface bridge | Ashay Narsale | 2022-06-28 |
| 11366762 | Cache filter | — | 2022-06-21 |
| 11340787 | Memory protocol | James A. Hall, Jr. | 2022-05-24 |
| 11314643 | Enhanced duplicate write data tracking for cache memory | — | 2022-04-26 |
| 11301383 | Managing processing of memory commands in a memory subsystem with a high latency backing store | Patrick A. La Fratta, Cagdas Dirik, Laurent Isenegger | 2022-04-12 |
| 11301380 | Sector-based tracking for a page cache | Ashay Narsale | 2022-04-12 |
| 11288214 | Command selection policy | Patrick A. La Fratta | 2022-03-29 |
| 11256437 | Data migration for memory operation | Paul Rosenfeld, Patrick A. La Fratta | 2022-02-22 |
| 11243889 | Cache architecture for comparing data on a single page | — | 2022-02-08 |
| 11237995 | Transaction identification | Frank F. Ross | 2022-02-01 |
| 11226770 | Memory protocol | Frank F. Ross | 2022-01-18 |
| 11188234 | Cache line data | Cagdas Dirik | 2021-11-30 |