Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6703326 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2004-03-09 |
| 6693048 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2004-02-17 |
| 6673726 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2004-01-06 |
| 6670289 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2003-12-30 |
| 6665207 | ROM embedded DRAM with dielectric removal/short | Casey Kurth, Scott J. Derner | 2003-12-16 |
| 6603693 | DRAM with bias sensing | Scott J. Derner, Casey Kurth | 2003-08-05 |
| 6545899 | ROM embedded DRAM with bias sensing | Scott J. Derner, Casey Kurth | 2003-04-08 |
| 6501188 | Method for improving a stepper signal in a planarized surface over alignment topography | William A. Stanton, Kunal R. Parekh | 2002-12-31 |
| 6492285 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2002-12-10 |
| 6472328 | Methods of forming an electrical contact to semiconductive material | Terry L. Gilton, Casey Kurth, Russ Meyer | 2002-10-29 |
| 6455400 | Semiconductor processing methods of forming silicon layers | Keith Smith | 2002-09-24 |
| 6407455 | Local interconnect using spacer-masked contact etch | Kunal R. Parekh | 2002-06-18 |
| 6391805 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2002-05-21 |
| 6387828 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2002-05-14 |
| 6383887 | Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits | Kunal R. Parekh, John K. Zahurak | 2002-05-07 |
| 6352946 | High-pressure anneal process for integrated circuits | Richard H. Lane | 2002-03-05 |
| RE37505 | Stacked capacitor construction | Guy T. Blalock | 2002-01-15 |
| 6309941 | Methods of forming capacitors | Kunal R. Parekh, John K. Zahurak | 2001-10-30 |
| 6306705 | Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits | Kunal R. Parekh, John K. Zahurak | 2001-10-23 |
| 6281131 | Methods of forming electrical contacts | Terry L. Gilton, Casey Kurth, Russ Meyer | 2001-08-28 |
| 6242816 | Method for improving a stepper signal in a planarized surface over alignment topography | William A. Stanton, Kunal R. Parekh | 2001-06-05 |
| 6207523 | Methods of forming capacitors DRAM arrays, and monolithic integrated circuits | Kunal R. Parekh, John K. Zahurak | 2001-03-27 |
| 6180485 | Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits | Kunal R. Parekh, John K. Zahurak | 2001-01-30 |
| 6166395 | Amorphous silicon interconnect with multiple silicon layers | Keith Smith | 2000-12-26 |
| 6153527 | Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material | Mark E. Jost | 2000-11-28 |