Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6144109 | Method for improving a stepper signal in a planarized surface over alignment topography | William A. Stanton, Kunal R. Parekh | 2000-11-07 |
| 6107189 | Method of making a local interconnect using spacer-masked contact etch | Kunal R. Parekh | 2000-08-22 |
| 6096626 | Semiconductor structures and semiconductor processing methods of forming silicon layers | Keith Smith | 2000-08-01 |
| 6037261 | Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material | Mark E. Jost | 2000-03-14 |
| 6002623 | Semiconductor memory with test circuit | Eric J. Stave | 1999-12-14 |
| 5932491 | Reduction of contact size utilizing formation of spacer material over resist pattern | Mark Fischer, William A. Stanton | 1999-08-03 |
| 5895274 | High-pressure anneal process for integrated circuits | Richard H. Lane | 1999-04-20 |
| 5892720 | Semiconductor memory with test circuit | Eric J. Stave | 1999-04-06 |
| 5739068 | Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material | Mark E. Jost | 1998-04-14 |
| 5684809 | Semiconductor memory with test circuit | Eric J. Stave | 1997-11-04 |
| 5300801 | Stacked capacitor construction | Guy T. Blalock | 1994-04-05 |
| 5238862 | Method of forming a stacked capacitor with striated electrode | Guy T. Blalock | 1993-08-24 |
| 5030587 | Method of forming substantially planar digit lines | Pierre C. Fazan | 1991-07-09 |