Issued Patents All Time
Showing 51–75 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7355387 | System and method for testing integrated circuit timing margins | — | 2008-04-08 |
| 7339838 | Method and apparatus for supplementary command bus | — | 2008-03-04 |
| 7330992 | System and method for read synchronization of memory modules | Joseph M. Jeddeloh | 2008-02-12 |
| 7284169 | System and method for testing write strobe timing margins in memory devices | Keith J. Lunzer | 2007-10-16 |
| 7277996 | Modified persistent auto precharge command protocol system and method for memory devices | Jeffery W. Janzen | 2007-10-02 |
| 7222325 | Method for modifying an integrated circuit | — | 2007-05-22 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules | — | 2007-02-20 |
| 7149841 | Memory devices with buffered command address bus | — | 2006-12-12 |
| 7139852 | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing | — | 2006-11-21 |
| 7124260 | Modified persistent auto precharge command protocol system and method for memory devices | Jeffery W. Janzen | 2006-10-17 |
| 7076678 | Method and apparatus for data transfer | — | 2006-07-11 |
| 7055012 | Latency reduction using negative clock edge and read flags | Jeff Janzen | 2006-05-30 |
| 6980042 | Delay line synchronizer apparatus and method | — | 2005-12-27 |
| 6910088 | Bus arbitration using monitored windows of time | — | 2005-06-21 |
| 6898648 | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing | — | 2005-05-24 |
| 6888760 | System and method for multiplexing data and data masking information on a data bus of a memory device | — | 2005-05-03 |
| 6880094 | Cas latency select utilizing multilevel signaling | — | 2005-04-12 |
| 6876589 | Method and apparatus for supplementary command bus | — | 2005-04-05 |
| 6851032 | Latency reduction using negative clock edge and read flags | Jeff Janzen | 2005-02-01 |
| 6804764 | Write clock and data window tuning based on rank select | Jim M. Dodd | 2004-10-12 |
| 6804750 | Technique for reducing memory latency during a memory request | — | 2004-10-12 |
| 6795931 | Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage | — | 2004-09-21 |
| 6771526 | Method and apparatus for data transfer | — | 2004-08-03 |
| 6763416 | Capturing read data | — | 2004-07-13 |
| 6732342 | Placing gates in an integrated circuit based upon drive strength | — | 2004-05-04 |