Issued Patents All Time
Showing 26–50 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8239607 | System and method for an asynchronous data buffer having buffer write and read pointers | — | 2012-08-07 |
| 8169841 | Strobe apparatus, systems, and methods | James B. Johnson, Jake Klier | 2012-05-01 |
| 8164375 | Delay line synchronizer apparatus and method | — | 2012-04-24 |
| 8065461 | Capturing read data | — | 2011-11-22 |
| 8010866 | Memory system and method using stacked memory device dice, and system using the memory system | Joseph M. Jeddeloh, James B. Johnson | 2011-08-30 |
| 8006057 | Memory devices with buffered command address bus | — | 2011-08-23 |
| 7978721 | Multi-serial interface stacked-die memory architecture | Joe M. Jeddeloh | 2011-07-12 |
| 7969815 | System and method for controlling timing of output signals | — | 2011-06-28 |
| 7855931 | Memory system and method using stacked memory device dice, and system using the memory system | Joseph M. Jeddeloh, James B. Johnson | 2010-12-21 |
| 7855928 | System and method for controlling timing of output signals | — | 2010-12-21 |
| 7835207 | Stacked device remapping and repair | Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles +1 more | 2010-11-16 |
| 7822904 | Capturing read data | — | 2010-10-26 |
| 7818601 | Method and apparatus for data transfer | — | 2010-10-19 |
| 7707473 | Integrated testing apparatus, systems, and methods | Jeffrey J. Rooney, Charles K. Snodgrass | 2010-04-27 |
| 7673094 | Memory devices with buffered command address bus | — | 2010-03-02 |
| 7619404 | System and method for testing integrated circuit timing margins | — | 2009-11-17 |
| 7605631 | Delay line synchronizer apparatus and method | — | 2009-10-20 |
| 7594088 | System and method for an asynchronous data buffer having buffer write and read pointers | — | 2009-09-22 |
| 7546435 | Dynamic command and/or address mirroring system and method for memory modules | — | 2009-06-09 |
| 7526704 | Testing system and method allowing adjustment of signal transmit timing | — | 2009-04-28 |
| 7519788 | System and method for an asynchronous data buffer having buffer write and read pointers | — | 2009-04-14 |
| 7516281 | On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes | — | 2009-04-07 |
| 7434081 | System and method for read synchronization of memory modules | Joseph M. Jeddeloh | 2008-10-07 |
| 7379382 | System and method for controlling timing of output signals | — | 2008-05-27 |
| 7355387 | System and method for testing integrated circuit timing margins | — | 2008-04-08 |