Issued Patents All Time
Showing 1,026–1,050 of 1,109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6208164 | Programmable logic array with vertical transistors | Wendell P. Noble | 2001-03-27 |
| 6201287 | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods | — | 2001-03-13 |
| 6198681 | Sense amplifier for low voltage memory arrays | — | 2001-03-06 |
| 6198168 | Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same | Joseph E. Geusic, Kie Y. Ahn | 2001-03-06 |
| 6191448 | Memory cell with vertical transistor and buried word and body lines | Wendell P. Noble, Kie Y. Ahn | 2001-02-20 |
| 6191470 | Semiconductor-on-insulator memory cell with buried word and body lines | Kie Y. Ahn | 2001-02-20 |
| 6191468 | Inductor with magnetic material layers | Kie Y. Ahn | 2001-02-20 |
| 6174784 | Technique for producing small islands of silicon on insulator | — | 2001-01-16 |
| 6166401 | Flash memory with microcrystalline silicon carbide film floating gate | — | 2000-12-26 |
| 6165828 | Structure and method for gated lateral bipolar transistors | Wendell P. Noble | 2000-12-26 |
| 6165836 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Wendell P. Noble | 2000-12-26 |
| 6163066 | Porous silicon dioxide insulator | Kie Y. Ahn | 2000-12-19 |
| 6156374 | Method of forming insulating material between components of an integrated circuit | Kie Y. Ahn | 2000-12-05 |
| 6156607 | Method for a folded bit line memory using trench plate capacitor cells with body bias contacts | Wendell P. Noble | 2000-12-05 |
| 6156604 | Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Wendell P. Noble | 2000-12-05 |
| 6153468 | Method of forming a logic array for a decoder | Wendell P. Noble | 2000-11-28 |
| 6150687 | Memory cell having a vertical transistor with buried source/drain and dual gates | Wendell P. Noble, Kie Y. Ahn | 2000-11-21 |
| 6150188 | Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same | Joseph E. Geusic, Kie Y. Ahn | 2000-11-21 |
| 6143616 | Methods of forming coaxial integrated circuitry interconnect lines | Joseph E. Geusic, Kie Y. Ahn | 2000-11-07 |
| 6143655 | Methods and structures for silver interconnections in integrated circuits | Paul A. Farrar, Kie Y. Ahn | 2000-11-07 |
| 6143636 | High density flash memory | Wendell P. Noble | 2000-11-07 |
| 6141260 | Single electron resistor memory device and method for use thereof | Kie Y. Ahn | 2000-10-31 |
| 6140181 | Memory using insulator traps | Joseph E. Geusic | 2000-10-31 |
| 6140877 | Low power supply CMOS differential amplifier topology | — | 2000-10-31 |
| 6141238 | Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same | Kie Y. Ahn, Wendell P. Noble, Alan R. Reinberg | 2000-10-31 |