Issued Patents All Time
Showing 1,076–1,100 of 1,109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6060754 | Circuit and method for gate-body structures in CMOS technology | Wendell P. Noble | 2000-05-09 |
| 6049496 | Circuit and method for low voltage, current sense amplifier | Wendell P. Noble | 2000-04-11 |
| 6049106 | Large grain single crystal vertical thin film polysilicon MOSFETs | — | 2000-04-11 |
| 6043527 | Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device | — | 2000-03-28 |
| 6031263 | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate | Kie Y. Ahn | 2000-02-29 |
| 6025627 | Alternate method and structure for improved floating gate tunneling devices | Joseph E. Geusic | 2000-02-15 |
| 6025225 | Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same | Joseph E. Geusic, Kie Y. Ahn | 2000-02-15 |
| 6025261 | Method for making high-Q inductive elements | Paul A. Farrar | 2000-02-15 |
| 6009018 | Differential flash memory cell and method for programming same | — | 1999-12-28 |
| 5995410 | Multiplication of storage capacitance in memory cells by using the Miller effect | — | 1999-11-30 |
| 5991225 | Programmable memory address decode array with vertical transistors | Wendell P. Noble | 1999-11-23 |
| 5989958 | Flash memory with microcrystalline silicon carbide film floating gate | — | 1999-11-23 |
| 5981350 | Method for forming high capacitance memory cells | Joseph E. Geusic, Kie Y. Ahn | 1999-11-09 |
| 5973356 | Ultra high density flash memory | Wendell P. Noble | 1999-10-26 |
| 5963469 | Vertical bipolar read access for low voltage memory cell | — | 1999-10-05 |
| 5959896 | Multi-state flash memory cell and method for programming single electron differences | — | 1999-09-28 |
| 5936274 | High density flash memory | Wendell P. Noble | 1999-08-10 |
| 5926740 | Graded anti-reflective coating for IC lithography | Kie Y. Ahn | 1999-07-20 |
| 5920121 | Methods and structures for gold interconnections in integrated circuits | Paul A. Farrar, Kie Y. Ahn | 1999-07-06 |
| 5914511 | Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts | Wendell P. Noble | 1999-06-22 |
| 5909618 | Method of making memory cell with vertical transistor and buried word and body lines | Wendell P. Noble, Kie Y. Ahn | 1999-06-01 |
| 5907170 | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Wendell P. Noble | 1999-05-25 |
| 5897351 | Method for forming merged transistor structure for gain memory cell | — | 1999-04-27 |
| 5886368 | Transistor with silicon oxycarbide gate and methods of fabrication and use | Joseph E. Geusic, Kie Y. Ahn | 1999-03-23 |
| 5879996 | Silicon-germanium devices for CMOS formed by ion implantation and solid phase epitaxial regrowth | — | 1999-03-09 |