Issued Patents All Time
Showing 1,001–1,025 of 1,109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6274937 | Silicon multi-chip module packaging with integrated passive components and method of making | Kie Y. Ahn | 2001-08-14 |
| 6261751 | Low temperature anti-reflective coating for IC lithography | Kie Y. Ahn | 2001-07-17 |
| 6255156 | Method for forming porous silicon dioxide insulators and related structures | Kie Y. Ahn | 2001-07-03 |
| 6255852 | Current mode signal interconnects and CMOS amplifier | Kie Y. Ahn | 2001-07-03 |
| 6251470 | Methods of forming insulating materials, and methods of forming insulating materials around a conductive component | Kie Y. Ahn | 2001-06-26 |
| 6249020 | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate | Kie Y. Ahn | 2001-06-19 |
| 6249191 | Monolithic integrated circuit oscillators, complementary metal oxide semiconductor (CMOS) voltage-controlled oscillators, integrated circuit oscillators, oscillator-forming methods, and oscillation methods | — | 2001-06-19 |
| 6249460 | Dynamic flash memory cells with ultrathin tunnel oxides | Luan C. Tran, Alan R. Reinberg, Joseph E. Geusic, Kie Y. Ahn, Paul A. Farrar +2 more | 2001-06-19 |
| 6245615 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Wendell P. Noble, Alan R. Reinberg | 2001-06-12 |
| 6246606 | Memory using insulator traps | Joseph E. Geusic | 2001-06-12 |
| 6242304 | Method and structure for textured surfaces in floating gate tunneling oxide devices | Joseph E. Geusic | 2001-06-05 |
| 6240622 | Integrated circuit inductors | Kie Y. Ahn | 2001-06-05 |
| 6238976 | Method for forming high density flash memory | Wendell P. Noble | 2001-05-29 |
| 6239684 | High-Q inductive elements | Paul A. Farrar | 2001-05-29 |
| 6235569 | Circuit and method for low voltage, voltage sense amplifier | Wendell P. Noble | 2001-05-22 |
| 6232705 | Field emitter arrays with gate insulator and cathode formed from single layer of polysilicon | Kie Y. Ahn | 2001-05-15 |
| 6232643 | Memory using insulator traps | Joseph E. Geusic | 2001-05-15 |
| 6229342 | Circuits and method for body contacted and backgated transistors | Wendell P. Noble | 2001-05-08 |
| 6225165 | High density SRAM cell with latched vertical transistors | Wendell P. Noble | 2001-05-01 |
| 6222778 | Single electron MOSFET memory device and method | Kie Y. Ahn | 2001-04-24 |
| 6222788 | Vertical gate transistors in pass transistor logic decode circuits | Kie Y. Ahn | 2001-04-24 |
| 6219299 | Programmable memory decode circuits with transistors with vertical gates | Kie Y. Ahn | 2001-04-17 |
| 6219237 | Structure and method for an electronic assembly | Joseph E. Geusic, Kie Y. Ahn | 2001-04-17 |
| 6211562 | Homojunction semiconductor devices with low barrier tunnel oxide contacts | Kie Y. Ahn | 2001-04-03 |
| 6211073 | Methods for making copper and other metal interconnections in integrated circuits | Kie Y. Ahn | 2001-04-03 |