Issued Patents All Time
Showing 801–825 of 1,109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6720655 | Multilevel interconnect structure with low-k dielectric | Kie Y. Ahn | 2004-04-13 |
| 6720221 | Structure and method for dual gate oxide thicknesses | Kie Y. Ahn | 2004-04-13 |
| 6710538 | Field emission display having reduced power requirements and method | Kie Y. Ahn | 2004-03-23 |
| 6710428 | Porous silicon oxycarbide integrated circuit insulator | Kie Y. Ahn | 2004-03-23 |
| 6709978 | Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer | Joseph E. Geusic, Kie Y. Ahn | 2004-03-23 |
| 6706597 | Method for textured surfaces in floating gate tunneling oxide devices | Joseph E. Geusic | 2004-03-16 |
| 6701607 | Integrated circuit inductors | Kie Y. Ahn | 2004-03-09 |
| 6700821 | Programmable mosfet technology and programmable address decode and correction | Wendell P. Noble, Eugene H. Cloud | 2004-03-02 |
| 6696912 | Integrated circuit inductor with a magnetic core | Kie Y. Ahn | 2004-02-24 |
| 6696360 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow | Kie Y. Ahn | 2004-02-24 |
| 6696330 | Methods, structures, and circuits for transistors with gate-to-body capacitive coupling | Wendell P. Noble | 2004-02-24 |
| 6689660 | 4 F2 folded bit line DRAM cell structure having buried bit and word lines | Wendell P. Noble, Kie Y. Ahn | 2004-02-10 |
| 6686766 | Technique to reduce reflections and ringing on CMOS interconnections | Kie Y. Ahn | 2004-02-03 |
| 6683337 | Dynamic memory based on single electron storage | Kie Y. Ahn | 2004-01-27 |
| 6680518 | Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods | — | 2004-01-20 |
| 6674672 | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits | Kie Y. Ahn | 2004-01-06 |
| 6674667 | Programmable fuse and antifuse and method therefor | — | 2004-01-06 |
| 6674167 | Multilevel copper interconnect with double passivation | Kie Y. Ahn, Jerome M. Eldridge | 2004-01-06 |
| 6670703 | Buried ground plane for high performance system modules | Kie Y. Ahn | 2003-12-30 |
| 6664806 | Memory address and decode circuits with ultra thin body transistors | Kie Y. Ahn | 2003-12-16 |
| 6664589 | Technique to control tunneling currents in DRAM capacitors, cells, and devices | Salman Akram | 2003-12-16 |
| 6661058 | Highly reliable gate oxide and method of fabrication | Kie Y. Ahn | 2003-12-09 |
| 6656813 | Low loss high Q inductor | Kie Y. Ahn | 2003-12-02 |
| 6654275 | SRAM cell with horizontal merged devices | — | 2003-11-25 |
| 6653208 | Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing | Kie Y. Ahn | 2003-11-25 |