Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10261876 | Memory management | Marco Dallabora, Emanuele Confalonieri, Paolo Amato, Danilo Caraccio | 2019-04-16 |
| 10146477 | Command queuing | Victor Y. Tsai, Danilo Caraccio, Neal A. Galbo, Robert Warren | 2018-12-04 |
| 10083751 | Data state synchronization | Marco Dallabora, Paolo Amato, Danilo Caraccio, Emanuele Confalonieri | 2018-09-25 |
| 10067890 | Apparatuses and methods for variable latency memory operations | Graziano Mirichigni, Luca Porzio | 2018-09-04 |
| 10068649 | Apparatuses and methods for performing multiple memory operations | Corrado Villa | 2018-09-04 |
| 9734097 | Apparatuses and methods for variable latency memory operations | Graziano Mirichigni, Luca Porzio | 2017-08-15 |
| 9696908 | Non-volatile memory, system, and method | Graziano Mirichigni | 2017-07-04 |
| 9685234 | Apparatuses and methods for performing multiple memory operations | Corrado Villa | 2017-06-20 |
| 9577611 | Controlling clock input buffers | Daniele Vimercati, Graziano Mirichigni | 2017-02-21 |
| 9454310 | Command queuing | Victor Y. Tsai, Danilo Caraccio, Neal A. Galbo, Robert Warren | 2016-09-27 |
| 9384830 | Apparatuses and methods for performing multiple memory operations | Corrado Villa | 2016-07-05 |
| 9224440 | Non-volatile memory, system, and method | Graziano Mirichigni | 2015-12-29 |
| 8832392 | Indexed register access for memory device | Marco Ferrario | 2014-09-09 |
| 8825979 | Non-volatile memory circuit, system, and method | Graziano Mirichigni | 2014-09-02 |
| 8824235 | Controlling clock input buffers | Daniele Vimercati, Graziano Mirichigni | 2014-09-02 |
| 8762656 | Temperature alert and low rate refresh for a non-volatile memory | Emanuele Confalonieri | 2014-06-24 |
| 8543787 | Non-volatile memory circuit, system, and method | Graziano Mirichigni | 2013-09-24 |
| 8539189 | Indexed register access for memory device | Marco Ferrario | 2013-09-17 |
| 8504759 | Method and devices for controlling power loss | Corrado Villa, Graziano Mirichigni | 2013-08-06 |
| 7916575 | Configurable latching for asynchronous memories | Emanuele Confalonieri, Chris Bueb, Graziano Mirichigni | 2011-03-29 |
| 7154803 | Redundancy scheme for a memory integrated circuit | Andrea Martinelli, Corrado Villa | 2006-12-26 |
| 6507534 | Column decoder circuit for page reading of a semiconductor memory | — | 2003-01-14 |