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Memory cell with a flat-topped floating gate structure |
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2020-06-30 |
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Non-volatile flash memory cell |
Sonu Daryanani, Bomy Chen |
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Memory cell with oxide cap and spacer layer for protecting a floating gate from a source implant |
Bomy Chen, Greg Stom, James Walls |
2020-01-28 |
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Floating gate spacer for controlling a source region formation in a memory cell |
James Walls, Sajid Kabeer |
2019-09-24 |
| 10347728 |
Memory cell with asymmetric word line and erase gate for decoupled program erase performance |
James Walls, Sonu Daryanani |
2019-07-09 |
| 10050131 |
Method of forming a polysilicon sidewall oxide region in a memory cell |
Jack T. Wong, Sajid Kabeer, Santosh Murali, Brad Kopp |
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| 9455037 |
EEPROM memory cell with low voltage read path and high voltage erase/write path |
Kent Hewitt, Jack T. Wong, Bomy Chen, Sonu Daryanani, Jeffrey A. Shields +1 more |
2016-09-27 |