Issued Patents All Time
Showing 101–125 of 169 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8836137 | Method for creating a 3D stacked multichip module | — | 2014-09-16 |
| 8815655 | Method for manufacturing semiconductor device | — | 2014-08-26 |
| 8811077 | Memory architecture of 3D array with improved uniformity of bit line capacitances | Chun-Hsiung Hung, Hang-Ting Lue | 2014-08-19 |
| 8759217 | Method for forming interlayer connectors to a stack of conductive layers | — | 2014-06-24 |
| 8759899 | Integration of 3D stacked IC device with peripheral circuits | Hang-Ting Lue, Yi-Hsuan Hsiao, Yen-Hao Shih | 2014-06-24 |
| 8704205 | Semiconductor structure with improved capacitance of bit line | Hang-Ting Lue, Kuang Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih | 2014-04-22 |
| 8692379 | Integrated circuit connector access region | — | 2014-04-08 |
| 8664689 | Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions | Hsiang-Lan Lung, Erh-Kun Lai, Yen-Hao Shih, Yi-Chou Chen | 2014-03-04 |
| 8659949 | Three-dimensional memory structure and method of operating the same hydride | — | 2014-02-25 |
| 8644077 | Memory device, manufacturing method and operating method of the same | Hang-Ting Lue | 2014-02-04 |
| 8643078 | Semiconductor structure and manufacturing method of the same | Hang-Ting Lue, Kuang Yeu Hsieh | 2014-02-04 |
| 8633099 | Method for forming interlayer connectors in a three-dimensional stacked IC device | Yen-Hao Shih, Teng-Hao Yeh, Chih-Wei Hu, Feng-Nien Tsai, Lo-Yueh Lin | 2014-01-21 |
| 8604555 | Semiconductor structure and manufacturing method of the same | Kuang Yeu Hsieh | 2013-12-10 |
| 8598032 | Reduced number of masks for IC device with stacked contact levels | Hang-Ting Lue | 2013-12-03 |
| 8574992 | Contact architecture for 3D memory array | Yen-Hao Shih, Hang-Ting Lue | 2013-11-05 |
| 8558394 | Chip stack structure and manufacturing method thereof | — | 2013-10-15 |
| 8541882 | Stacked IC device with recessed conductive layers adjacent to interlevel conductors | Yan-Ru Chen, Lo-Yueh Lin | 2013-09-24 |
| 8536559 | Phase change memory | — | 2013-09-17 |
| 8503213 | Memory architecture of 3D array with alternating memory string orientation and string select structures | Hang-Ting Lue | 2013-08-06 |
| 8492216 | Semiconductor structure with contact structure and manufacturing method of the same | — | 2013-07-23 |
| 8445313 | Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process | Matthew J. Breitwisch, Chieh-Fang Chen, Eric A. Joseph, Chung H. Lam, Michael F. Lofaro +3 more | 2013-05-21 |
| 8383512 | Method for making multilayer connection structure | Hang-Ting Lue, Hong-Ji Lee, Chin-Cheng Yang | 2013-02-26 |
| 8363476 | Memory device, manufacturing method and operating method of the same | Hang-Ting Lue | 2013-01-29 |
| 8344347 | Multi-layer electrode structure | — | 2013-01-01 |
| 8304911 | Semiconductor structure and manufacturing method of the same | Hang-Ting Lue, Yi-Hsuan Hsiao | 2012-11-06 |