Issued Patents All Time
Showing 1–25 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8378414 | Low leakage FINFETs | Volker Dudek, Michael Graf | 2013-02-19 |
| 8138578 | Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device | Bryan D. Sendelweck | 2012-03-20 |
| 7848070 | Electrostatic discharge (ESD) protection structure and a circuit using the same | Stefan Schwantes, Michael Graf, Volker Dudek, Irwin Rathbun, Peter Grombach +1 more | 2010-12-07 |
| 7642181 | LOCOS self-aligned twin well with a co-planar silicon surface | Irwin Rathbun, Bryan D. Sendelweck, Thomas S. Moss, III | 2010-01-05 |
| 7629649 | Method and materials to control doping profile in integrated circuit substrate material | Thomas S. Moss, III, Mark Good | 2009-12-08 |
| 7541250 | Method for forming a self-aligned twin well region with simplified processing | Bryan D. Sendelweck | 2009-06-02 |
| 7521312 | Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device | Bryan D. Sendelweck | 2009-04-21 |
| 7435661 | Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation | Eric Brown | 2008-10-14 |
| 7407851 | DMOS device with sealed channel processing | Irwin Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek | 2008-08-05 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same | Stefan Schwantes, Michael Graf, Volker Dudek, Irwin Rathbun, Peter Grombach +1 more | 2008-07-22 |
| 7348256 | Methods of forming reduced electric field DMOS using self-aligned trench isolation | Volker Dudek, Michael Graf | 2008-03-25 |
| 7230342 | Registration mark within an overlap of dopant regions | Franz Dietz, Volker Dudek, Michael Graf, Stefan Schwantes | 2007-06-12 |
| 6885078 | Circuit isolation utilizing MeV implantation | Donald M. Bartlett, Randall Mason | 2005-04-26 |
| 6806162 | Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device | Gail D. Shelton | 2004-10-19 |
| 6794310 | Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof | Todd A. Randazzo | 2004-09-21 |
| 6614097 | Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device | Gail D. Shelton | 2003-09-02 |
| 6527867 | Method for enhancing anti-reflective coatings used in photolithography of electronic devices | Kunal N. Taravade, Gail D. Shelton | 2003-03-04 |
| 6522006 | Low dielectric constant material in integrated circuit | Derryl D. J. Allman, Kenneth P. Fuchs, Samuel C. Gioia | 2003-02-18 |
| 6522005 | Integrated circuit device comprising low dielectric constant material for reduced cross talk | Derryl D. J. Allman, Kenneth P. Fuchs, Samuel C. Gioia | 2003-02-18 |
| 6504250 | Integrated circuit device with reduced cross talk | Derryl D. J. Allman, Kenneth P. Fuchs, Samuel C. Gioia | 2003-01-07 |
| 6504249 | Integrated circuit device with reduced cross talk | Derryl D. J. Allman, Kenneth P. Fuchs, Samuel C. Gioia | 2003-01-07 |
| 6448653 | Method for using low dielectric constant material in integrated circuit fabrication | Derryl D. J. Allman, Kenneth P. Fuchs, Samuel C. Gioia | 2002-09-10 |
| 6441419 | Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same | Gregory A. Johnson, Kunal N. Taravade | 2002-08-27 |
| 6383332 | Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint | Gail D. Shelton | 2002-05-07 |
| 6358819 | Dual gate oxide process for deep submicron ICS | Gail D. Shelton | 2002-03-19 |