Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7176082 | Analog capacitor in dual damascene process | Todd A. Randazzo, John D. Walker | 2007-02-13 |
| 7118985 | Method of forming a metal-insulator-metal capacitor in an interconnect cavity | Derryl D. J. Allman | 2006-10-10 |
| 6822282 | Analog capacitor in dual damascene process | Todd A. Randazzo, John D. Walker | 2004-11-23 |
| 6596579 | Method of forming analog capacitor dual damascene process | Todd A. Randazzo, John D. Walker | 2003-07-22 |
| 6522005 | Integrated circuit device comprising low dielectric constant material for reduced cross talk | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2003-02-18 |
| 6522006 | Low dielectric constant material in integrated circuit | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2003-02-18 |
| 6504250 | Integrated circuit device with reduced cross talk | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2003-01-07 |
| 6504202 | Interconnect-embedded metal-insulator-metal capacitor | Derryl D. J. Allman | 2003-01-07 |
| 6504249 | Integrated circuit device with reduced cross talk | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2003-01-07 |
| 6448653 | Method for using low dielectric constant material in integrated circuit fabrication | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2002-09-10 |
| 6358837 | Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit | Gayle W. Miller | 2002-03-19 |
| 6208029 | Integrated circuit device with reduced cross talk | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 2001-03-27 |
| 6071817 | Isolation method utilizing a high pressure oxidation | Derryl D. J. Allman | 2000-06-06 |
| 6057571 | High aspect ratio, metal-to-metal, linear capacitor for an integrated circuit | Gayle W. Miller | 2000-05-02 |
| 6010963 | Global planarization using SOG and CMP | Derryl D. J. Allman | 2000-01-04 |
| 5543361 | Process for forming titanium silicide local interconnect | Steven S. Lee, Gayle W. Miller | 1996-08-06 |
| 5447880 | Method for forming an amorphous silicon programmable element | Steven S. Lee, Gayle W. Miller | 1995-09-05 |
| 5443996 | Process for forming titanium silicide local interconnect | Steven S. Lee, Gayle W. Miller | 1995-08-22 |
| 5438022 | Method for using low dielectric constant material in integrated circuit fabrication | Derryl D. J. Allman, Gayle W. Miller, Samuel C. Gioia | 1995-08-01 |
| 5312512 | Global planarization using SOG and CMP | Derryl D. J. Allman | 1994-05-17 |