Issued Patents All Time
Showing 51–75 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11165430 | Majority logic gate based sequential circuit | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-11-02 |
| 11139270 | Artificial intelligence processor with three-dimensional stacked memory | Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2021-10-05 |
| 11025254 | Linear input and non-linear output threshold logic gate | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-06-01 |
| 11018672 | Linear input and non-linear output majority logic gate | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-05-25 |
| 11012076 | Linear input and non-linear output majority logic gate with and/or function | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-05-18 |
| 10998025 | High-density low voltage non-volatile differential memory bit-cell with shared plate-line | Sasikanth Manipatruni, Rajeev Kumar Dokania | 2021-05-04 |
| 10951213 | Majority logic gate fabrication | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-03-16 |
| 10944404 | Low power ferroelectric based majority logic gate adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2021-03-09 |
| 10847201 | High-density low voltage non-volatile differential memory bit-cell with shared plate line | Sasikanth Manipatruni, Rajeev Kumar Dokania | 2020-11-24 |
| 9356224 | Thin film bismuth iron oxides useful for piezoelectric devices | Robert J. Zeches, Lane W. Martin | 2016-05-31 |
| 8222510 | Complex oxides useful for thermoelectric energy conversion | Arunava Majumdar, Choongho Yu, Matthew L. Scullin, Mark Huijben | 2012-07-17 |
| 7696549 | Bismuth ferrite films and devices grown on silicon | — | 2010-04-13 |
| 6908802 | Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same | — | 2005-06-21 |
| 6861798 | Tailored spacer wall coatings for reduced secondary electron emission | Lawrence S. Pan, Donald R. Schropp, Jr., Vasil M. Chakarov, John K. O'Reilly, George B. Hopple +6 more | 2005-03-01 |
| 6781176 | Conductively doped strontium titanate barrier intermediate a silicon underlayer and an epitaxial metal oxide film | — | 2004-08-24 |
| 6642539 | Epitaxial template and barrier for the integration of functional thin film metal oxide heterostructures on silicon | Darrell G. Schlom | 2003-11-04 |
| 6610549 | Amorphous barrier layer in a ferroelectric memory cell | Sanjeev Aggarwal | 2003-08-26 |
| 6541281 | Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same | — | 2003-04-01 |
| 6518609 | Niobium or vanadium substituted strontium titanate barrier intermediate a silicon underlayer and a functional metal oxide film | — | 2003-02-11 |
| 6482538 | Microelectronic piezoelectric structure and method of forming the same | Yu-Po Wang, Jeffrey M. Finder, Zhiyi Yu, Ravindranath Droopad, Kurt Eisenbeiser | 2002-11-19 |
| 6426536 | Double layer perovskite oxide electrodes | James Misewich, Alejandro G. Schrott | 2002-07-30 |
| 6274388 | Annealing of a crystalline perovskite ferroelectric cell | Sanjeev Aggarwal, Anil M. Dhote | 2001-08-14 |
| 6265230 | Methods to cure the effects of hydrogen annealing on ferroelectric capacitors | Sanjeev Aggarwal, Scott Robert Perusse | 2001-07-24 |
| 6194754 | Amorphous barrier layer in a ferroelectric memory cell | Sanjeev Aggarwal | 2001-02-27 |
| 6115281 | Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors | Sanjeev Aggarwal, Scott Robert Perusse | 2000-09-05 |