Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11710416 | Multi-dimensional flight release efficiency evaluation method | Jibo HUANG, Hui Ding, Jing Tian, Ming Tong, Bin Dong +2 more | 2023-07-25 |
| 11488838 | Semiconductor device having an embedded conductive layer for power/ground planes in Fo-eWLB | Yaojian Lin, Kang Chen | 2022-11-01 |
| 11250241 | Face image processing methods and apparatuses, and electronic devices | Qiong Yan, Zhanpeng Zhang, Tianhan WEI, Guijie Wang, Jianbo Liu +3 more | 2022-02-15 |
| 11132824 | Face image processing method and apparatus, and electronic device | Guijie Wang, Jianbo Liu, Canbin WANG, Chenghao Liu, Ting Liao +2 more | 2021-09-28 |
| 10972709 | Image processing method and apparatus, electronic device, and computer storage medium | Junfan Lin, Chao Dong, Juan Lin, Haoran Wang, Ligen DAI +6 more | 2021-04-06 |
| 10741416 | Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB | Yaojian Lin, Kang Chen | 2020-08-11 |
| 9685350 | Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB | Yaojian Lin, Kang Chen | 2017-06-20 |
| 9620557 | Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region | Seng Guan Chow, Lee Sun Lim, Rui Huang, Ma Phoo Pwint Hlaing | 2017-04-11 |
| 7968445 | Semiconductor package with passivation island for reducing stress on solder bumps | Yaojian Lin | 2011-06-28 |
| 7667335 | Semiconductor package with passivation island for reducing stress on solder bumps | Yaojian Lin | 2010-02-23 |