Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D847178 | Display screen with graphical user interface | Kaoru Kato, Chisa Nagai | 2019-04-30 |
| D817978 | Display screen with graphical user interface | Kaoru Kato, Chiaki Hirai, Yukiko Morimoto | 2018-05-15 |
| 9507392 | Information processing system, and its power-saving control method and device | Jun Okitsu, Yuki Kuroda, Eiichi Suzuki, Takeshi Kato, Tatsuya Saito | 2016-11-29 |
| 9189039 | Information processing system, operation management method of information processing system, and data center | Jun Okitsu, Masayoshi Mase, Tatsuya Saito | 2015-11-17 |
| 8813070 | Data processor with interfaces for peripheral devices | Yuki Kondoh | 2014-08-19 |
| 8706996 | Data processor | Yuki Kondoh | 2014-04-22 |
| 7469281 | Network topology management system, management apparatus, management method, management program, and storage media that records management program | Yasunori Kaneda | 2008-12-23 |
| 6041399 | VLIW system with predicated instruction execution for individual instruction fields | Koichi Terada, Keiji Kojima, Yoshifumi Fujikawa, Kiyokazu Nishioka | 2000-03-21 |
| 5893143 | Parallel processing unit with cache memories storing NO-OP mask bits for instructions | Kazuhiko Tanaka, Keiji Kojima, Kiyokazu Nishioka, Yoshifumi Fujikawa, Masao Ishiguro | 1999-04-06 |
| 5872964 | Comparison operating unit and graphic operating system | Masao Ishiguro, Keiji Kojima, Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa | 1999-02-16 |
| 5870618 | Processor and data processor | Yoshifumi Fujikawa, Keiji Kojima, Kiyokazu Nishioka, Kazuhiko Tanaka, Masao Ishiguro | 1999-02-09 |
| 5815696 | Pipeline processor including interrupt control system for accurately perform interrupt processing even applied to VLIW and delay branch instruction in delay slot | Kazuhiko Tanaka, Keiji Kojima, Kiyokazu Nishioka, Yoshiki Kurokawa | 1998-09-29 |
| 5517664 | RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing | Tan Watanabe, Keiichi Kurakazu, Yugo Kashiwagi, Keisuke Toyama | 1996-05-14 |
| 5307502 | Data processing system having multiple register management for call and return operations | Tan Watanabe, Keiichi Kurakazu, Yugo Kashiwagi, Keisuke Toyama | 1994-04-26 |
| 5293594 | Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups | Shunpei Kawasaki, Tan Watanabe, Kousuke Sakoda | 1994-03-08 |
| 5179685 | Information processing apparatus | — | 1993-01-12 |
| 5065353 | Adder control method and adder control circuit | Masahiro Kainaga | 1991-11-12 |
| 5043869 | Storage area structure in information processor | Norihisa Suzuki, Shumpei Kawasaki | 1991-08-27 |