Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6996700 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2006-02-07 |
| 6873324 | Data processing method, recording medium and data processing apparatus | Yasuhiko Saito, Koji Yamada | 2005-03-29 |
| 6343357 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2002-01-29 |
| 6272620 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-08-07 |
| 6253308 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-06-26 |
| 6205535 | Branch instruction having different field lengths for unconditional and conditional displacements | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-03-20 |
| 6131154 | Microcomputer having variable bit width area for displacement | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-10-10 |
| 6122724 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-09-19 |
| 6055627 | Compiling method of accessing a multi-dimensional array and system therefor | Ichiro Kyushima | 2000-04-25 |
| 5991545 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-11-23 |
| 5969976 | Division circuit and the division method thereof | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-10-19 |
| 5682545 | Microcomputer having 16 bit fixed length instruction format | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1997-10-28 |
| 5546559 | Cache reuse control system having reuse information field in each cache entry to indicate whether data in the particular entry has higher or lower probability of reuse | Ichiro Kyushima | 1996-08-13 |
| 5214775 | Hierarchy structured memory system contained in a multiprocessor system | Masaharu Yabushita, Hidehiko Akita | 1993-05-25 |
| 5065353 | Adder control method and adder control circuit | Tohru Nojiri | 1991-11-12 |
| 4692896 | Method of processing a plurality of code systems | Kousuke Sakoda, Hidehiko Akita, Fumiya Murata, Yoshitake Nakaosa | 1987-09-08 |
| 4491912 | Data processing system with improved microsubroutine facility | Kousuke Sakoda, Hiroaki Nakanishi | 1985-01-01 |