Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520178 | Methods and apparatus for designing and constructing dual write memory circuits with voltage assist | Sundar Iyer, Shang-Tse Chuang | 2016-12-13 |
| 9390212 | Methods and apparatus for synthesizing multi-port memory circuits | Sundar Iyer, Shang-Tse Chuang, Sanjeev Joshi, Adam Kablanian | 2016-07-12 |
| 9336862 | Sense amp activation according to word line common point | Myung-Gyoo Won, Heechoul Park | 2016-05-10 |
| 9281028 | Method and circuit for glitch reduction in memory read latch circuit | TaeJin Pyon, Yong Qin | 2016-03-08 |
| 9147466 | Methods and apparatus for designing and constructing dual write memory circuits with voltage assist | Sundar Iyer, Shang-Tse Chuang | 2015-09-29 |
| 9058860 | Methods and apparatus for synthesizing multi-port memory circuits | Sundar Iyer, Shang-Tse Chuang, Sanjeev Joshi, Adam Kablanian | 2015-06-16 |
| 8902672 | Methods and apparatus for designing and constructing multi-port memory circuits | Sundar Iyer, Shang-Tse Chuang, Sanjeev Joshi, Adam Kablanian, Kartik Mohanram | 2014-12-02 |
| 8760958 | Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist | Sundar Iyer, Shang-Tse Chuang | 2014-06-24 |