Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229589 | Method and apparatus for scheduling matrix operations in digital processing systems | Sharad Vasantrao Chole, Siyad Chih-Hua Ma | 2025-02-18 |
| 12182717 | Feature extraction with a convolutional neural network | Sharad Vasantrao Chole, Siyad Chih-Hua Ma | 2024-12-31 |
| 12141226 | Systems and processes for organizing and controlling multiple matrix processor circuits | Siyad Chih-Hua Ma, Sharad Vasantrao Chole | 2024-11-12 |
| 12008463 | Methods and apparatus for accessing external memory in a neural network processing system | Siyad Chih-Hua Ma, Sharad Vasantrao Chole | 2024-06-11 |
| 11983616 | Methods and apparatus for constructing digital circuits for performing matrix operations | Sharad Vasantrao Chole, Siyad Chih-Hua Ma | 2024-05-14 |
| 11151416 | Method and apparatus for efficiently processing convolution neural network operations | Sharad Vasantrao Chole, Siyad Chih-Hua Ma | 2021-10-19 |
| 10042573 | High speed memory systems and methods for designing hierarchical memory systems | Sundar Iyer | 2018-08-07 |
| 9965211 | Dynamic packet buffers with consolidation of low utilized memory banks | Sharad Vasantrao Chole, Georges Akis, Felice Bonardi, Rong Pan | 2018-05-08 |
| 9678669 | Hierarchical memory system compiler | Sundar Iyer, Sanjeev Joshi | 2017-06-13 |
| 9520178 | Methods and apparatus for designing and constructing dual write memory circuits with voltage assist | Sundar Iyer, Thu Nguyen | 2016-12-13 |
| 9442846 | High speed memory systems and methods for designing hierarchical memory systems | Sundar Iyer | 2016-09-13 |
| 9390212 | Methods and apparatus for synthesizing multi-port memory circuits | Sundar Iyer, Thu Nguyen, Sanjeev Joshi, Adam Kablanian | 2016-07-12 |
| 9293187 | Methods and apparatus for refreshing digital memory circuits | Sundar Iyer | 2016-03-22 |
| 9280464 | System and method for simultaneously storing and reading data from a memory system | Sundar Iyer | 2016-03-08 |
| 9147466 | Methods and apparatus for designing and constructing dual write memory circuits with voltage assist | Sundar Iyer, Thu Nguyen | 2015-09-29 |
| 9063876 | System and method for simultaneously storing and read data from a memory system | Sundar Iyer | 2015-06-23 |
| 9058860 | Methods and apparatus for synthesizing multi-port memory circuits | Sundar Iyer, Thu Nguyen, Sanjeev Joshi, Adam Kablanian | 2015-06-16 |
| 8935507 | System and method for storing multiple copies of data in a high speed memory system | Sundar Iyer | 2015-01-13 |
| 8902672 | Methods and apparatus for designing and constructing multi-port memory circuits | Sundar Iyer, Thu Nguyen, Sanjeev Joshi, Adam Kablanian, Kartik Mohanram | 2014-12-02 |
| 8838934 | System and method for storing data in a virtualized memory system with destructive reads | Sundar Iver | 2014-09-16 |
| 8760958 | Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist | Sundar Iyer, Thu Nguyen | 2014-06-24 |
| 8677072 | System and method for reduced latency caching | Sundar Iyer | 2014-03-18 |
| 8589851 | Intelligent memory system compiler | Sundar Iyer, Sanjeev Joshi | 2013-11-19 |
| 8504796 | System and method for storing data in a virtualized high speed memory system with an integrated memory mapping table | Sundar Iyer | 2013-08-06 |
| 8433880 | System and method for storing data in a virtualized high speed memory system | Sundar Iyer | 2013-04-30 |