Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12328880 | Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency | Navneet Jain, Bipul C. Paul | 2025-06-10 |
| 12293086 | Apparatus and method for providing high throughput memory responses | Bipul C. Paul | 2025-05-06 |
| 12087384 | Bias voltage generation circuit for memory devices | Ming Yin, Bipul C. Paul, Nishtha Gaul | 2024-09-10 |
| 11635958 | Multi-port register file for partial-sum accumulation | Vivek Raj, Gregory A. Northrop, Shivraj G. Dharne | 2023-04-25 |
| 11587601 | Apparatus and method for controlled transmitting of read pulse and write pulse in memory | Bipul C. Paul | 2023-02-21 |
| 11119691 | Method and apparatus to perform a function level reset in a memory controller | Balakrishnan Sundararaman, Chris Randall Stone, Charles Edward Peet, Jr., Allen Vestal, Siddharth Kumar | 2021-09-14 |
| 11113063 | Method and apparatus to control the use of hierarchical branch predictors based on the effectiveness of their results | James David Dundas, Xiaoxin Fan, Madhu Saravana Sibi Govindan | 2021-09-07 |
| 10620832 | Method and apparatus to abort a command | Chris Randall Stone, Balakrishnan Sundararaman | 2020-04-14 |
| 10572180 | Method and apparatus to perform a function level reset in a memory controller | Balakrishnan Sundararaman, Chris Randall Stone, Charles Edward Peet, Jr., Allen Vestal, Siddharth Kumar | 2020-02-25 |
| 10564865 | Lockless parity management in a distributed data storage system | Mark Ish, Anant Baderdinni, Balakrishnan Sundararaman | 2020-02-18 |
| 10310975 | Cache offload based on predictive power parameter | Balakrishnan Sundararaman, Mark Ish, Siddhartha Panda, Bagavathy Raj Arunachalam | 2019-06-04 |
| 10282103 | Method and apparatus to delete a command queue | Chris Randall Stone, Balakrishnan Sundararaman, Charles Edward Peet, Jr. | 2019-05-07 |
| 10169232 | Associative and atomic write-back caching system and method for storage subsystem | Horia Simionescu, Balakrishnan Sundararaman, Larry Stephen King, Mark Ish, Shailendra Aulakh | 2019-01-01 |
| 10061655 | Volatile cache reconstruction after power failure | Balakrishnan Sundararaman, Mark Ish | 2018-08-28 |
| 9996262 | Method and apparatus to abort a command | Chris Randall Stone, Balakrishnan Sundararaman | 2018-06-12 |
| 9160684 | Dynamic updating of scheduling hierarchy in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier, Allen Vestal | 2015-10-13 |
| 8869150 | Local messaging in a scheduling hierarchy in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier, Allen Vestal | 2014-10-21 |
| 8869156 | Speculative task reading in a traffic manager of a network processor | Shailendra Aulakh, Balakrishnan Sundararaman | 2014-10-21 |
| 8869151 | Packet draining from a scheduling hierarchy in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier, Shailendra Aulakh | 2014-10-21 |
| 8848723 | Scheduling hierarchy in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier, Shailendra Aulakh | 2014-09-30 |
| 8843682 | Hybrid address mutex mechanism for memory accesses in a network processor | — | 2014-09-23 |
| 8837501 | Shared task parameters in a scheduler of a network processor | Balakrishnan Sundararaman, Shailendra Aulakh, David P. Sonnier | 2014-09-16 |
| 8638805 | Packet draining from a scheduling hierarchy in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier, Shailendra Aulakh, Allen Vestal | 2014-01-28 |
| 8576862 | Root scheduling algorithm in a network processor | David P. Sonnier, Balakrishnan Sundararaman | 2013-11-05 |
| 8565250 | Multithreaded, superscalar scheduling in a traffic manager of a network processor | Balakrishnan Sundararaman, David P. Sonnier | 2013-10-22 |