Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12401605 | Communication fabric structures for increased bandwidth | Sergio Kolor, Dan Darel, Lior Zimet, Lital Levy-Rubin, Opher Kahn +3 more | 2025-08-26 |
| 12399830 | Scalable system on a chip | Per Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota +6 more | 2025-08-26 |
| 12007895 | Scalable system on a chip | Per Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota +6 more | 2024-06-11 |
| 11748284 | Systems and methods for arbitrating traffic in a bus | Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Benjamin K. Dodge +1 more | 2023-09-05 |
| 11675722 | Multiple independent on-chip interconnect | Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan Redshaw +8 more | 2023-06-13 |
| 11093425 | Systems and methods for arbitrating traffic in a bus | Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Benjamin K. Dodge +1 more | 2021-08-17 |
| 10963172 | Systems and methods for providing a back pressure free interconnect | Nachiappan Chidambaram Nachiappan, David L. Trawick, Yiu Chun Tse, Deniz Balkan, Hengsheng Geng +3 more | 2021-03-30 |
| 10965478 | Systems and methods for performing link disconnect | Hengsheng Geng | 2021-03-30 |
| 10649922 | Systems and methods for scheduling different types of memory requests with varying data sizes | Jaideep Dastidar, Yiu Chun Tse | 2020-05-12 |
| 10423558 | Systems and methods for controlling data on a bus using latency | Yiu Chun Tse, David L. Trawick, Hengsheng Geng, Jaideep Dastidar, Vinodh R. Cuppu +1 more | 2019-09-24 |
| 10255218 | Systems and methods for maintaining specific ordering in bus traffic | Yiu Chun Tse, Deniz Balkan, Vinodh R. Cuppu, Jaideep Dastidar, Hengsheng Geng | 2019-04-09 |