Issued Patents All Time
Showing 1–25 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10734383 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2020-08-04 |
| 10727252 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Jim Mali, Carole Lambert | 2020-07-28 |
| 10658385 | Cross-coupled transistor circuit defined on four gate electrode tracks | Jim Mali, Carole Lambert | 2020-05-19 |
| 10651200 | Cross-coupled transistor circuit defined on three gate electrode tracks | Jim Mali, Carole Lambert | 2020-05-12 |
| 10446536 | Cell circuit and layout with linear finfet structures | — | 2019-10-15 |
| 10230377 | Circuitry and layouts for XOR and XNOR logic | — | 2019-03-12 |
| 10217763 | Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid | Michael C. Smayling | 2019-02-26 |
| 10186523 | Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid | Michael C. Smayling | 2019-01-22 |
| 10141335 | Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures | Michael C. Smayling | 2018-11-27 |
| 10141334 | Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures | Michael C. Smayling | 2018-11-27 |
| 10074640 | Integrated circuit cell library for multiple patterning | Michael C. Smayling | 2018-09-11 |
| 10020321 | Cross-coupled transistor circuit defined on two gate electrode tracks | Jim Mali, Carole Lambert | 2018-07-10 |
| 9917056 | Coarse grid design methods and structures | Michael C. Smayling | 2018-03-13 |
| 9910950 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same | Jonathan R. Quandt, Dhrumil Gandhi | 2018-03-06 |
| 9905576 | Semiconductor chip including region having rectangular-shaped gate structures and first metal structures | Michael C. Smayling | 2018-02-27 |
| 9871056 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Jim Mali, Carole Lambert | 2018-01-16 |
| 9859277 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2018-01-02 |
| 9779200 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2017-10-03 |
| 9754878 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Stephen Kornachuk, James Mali, Carole Lambert, Brian Reed | 2017-09-05 |
| 9741719 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2017-08-22 |
| 9711495 | Oversized contacts and vias in layout defined by linearly constrained topology | — | 2017-07-18 |
| 9704845 | Methods for linewidth modification and apparatus implementing the same | Michael C. Smayling | 2017-07-11 |
| 9673825 | Circuitry and layouts for XOR and XNOR logic | — | 2017-06-06 |
| 9633987 | Integrated circuit cell library for multiple patterning | Michael C. Smayling | 2017-04-25 |
| 9595515 | Semiconductor chip including integrated circuit defined within dynamic array section | Michael C. Smayling | 2017-03-14 |