RB

Robert Beers

IN Intel: 23 patents #1,721 of 30,777Top 6%
Overall (All Time): #176,353 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12197357 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2025-01-14
12189550 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2025-01-07
11741030 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2023-08-29
11269793 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2022-03-08
10268583 High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier Robert G. Blankenship, Robert J. Safranek, Jeff Willey, Robert A. Maddox, Aaron T. Spink 2019-04-23
10248591 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2019-04-02
10120774 Coherence protocol tables Yuvraj S. Dhillon 2018-11-06
10019366 Satisfying memory ordering requirements between partial reads and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek, James Vash 2018-07-10
9703712 Satisfying memory ordering requirements between partial reads and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek, James Vash 2017-07-11
9626321 High performance interconnect Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Darren S. Jue +18 more 2017-04-18
9058271 Satisfying memory ordering requirements between partial reads and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek, James Vash 2015-06-16
8694736 Satisfying memory ordering requirements between partial reads and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek, James Vash 2014-04-08
8250311 Satisfying memory ordering requirements between partial reads and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek, James Vash 2012-08-21
8205045 Satisfying memory ordering requirements between partial writes and non-snoop accesses Ching-Tsun Chou, Robert J. Safranek 2012-06-19
8171095 Speculative distributed conflict resolution for a cache coherency protocol Herbert Hum, James R. Goodman, Rajnish Ghughal 2012-05-01
7917646 Speculative distributed conflict resolution for a cache coherency protocol Herbert Hum, James R. Goodman, Rajnish Ghughal 2011-03-29
7836144 System and method for a 3-hop cache coherency protocol Phanindra Kumar Mannava, Seungjoon Park, Brannon Batson 2010-11-16
7752397 Repeated conflict acknowledgements in a cache coherency protocol Aaron T. Spink 2010-07-06
7721050 Re-snoop for conflict resolution in a cache coherency protocol Herbert Hum 2010-05-18
7536515 Repeated conflict acknowledgements in a cache coherency protocol Aaron T. Spink 2009-05-19
7506108 Requester-generated forward for late conflicts in a cache coherency protocol Herbert Hum 2009-03-17
7434006 Non-speculative distributed conflict resolution for a cache coherency protocol Herbert Hum, James R. Goodman 2008-10-07
6954829 Non-speculative distributed conflict resolution for a cache coherency protocol Herbert Hum, James R. Goodman 2005-10-11