| 10089238 |
Method and apparatus for a shared cache with dynamic partitioning |
Subbarao Palacharla, Moinul Khan, Alain Artieri, Kedar Bhole, Vinod Chamarty +5 more |
2018-10-02 |
| 9734070 |
System and method for a shared cache with adaptive partitioning |
Alain Artieri, Subbarao Palacharla, Laurent Moll, Kedar Bhole, Vinod Chamarty |
2017-08-15 |
| 9612970 |
Method and apparatus for flexible cache partitioning by sets and ways into component caches |
Subbarao Palacharla, Moinul Khan, Alain Artieri, Kedar Bhole, Vinod Chamarty +1 more |
2017-04-04 |
| 9437278 |
Low latency synchronization scheme for mesochronous DDR system |
Edwin Jose, Michael Drop, Xuhao Huang, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy |
2016-09-06 |
| 9123408 |
Low latency synchronization scheme for mesochronous DDR system |
Edwin Jose, Michael Drop, Xuhao Huang, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy |
2015-09-01 |
| 8325525 |
Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals |
Jian Mao |
2012-12-04 |
| 8098539 |
Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation |
Michael Drop, Jian Mao |
2012-01-17 |
| 7804735 |
Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals |
Jian Mao |
2010-09-28 |
| 6754509 |
Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory |
Safi Khan, Sanjay Jha, Albert Scott Ludwin, Mehraban Iraninejad, Chauhung Lee +2 more |
2004-06-22 |
| 6735454 |
Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode |
Nicholas Yu, Kenneth D. Easton |
2004-05-11 |