Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6266807 | Method and system for executing instructions in an application-specific microprocessor | Franz Steininger, Jean Casteres | 2001-07-24 |
| 5687349 | Data processor with branch target address cache and subroutine return address cache and method of operation | — | 1997-11-11 |
| 5606682 | Data processor with branch target address cache and subroutine return address cache and method of operation | — | 1997-02-25 |
| 5572535 | Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design | Carl Preston Pixley, Hyunwoo Cho, Bernard Plessier, Jesse R. Wilson | 1996-11-05 |
| 5185694 | Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies | Robin W. Edenfield, Russell A. Reininger, William B. Ledbetter, Jr., Van B. Shahan | 1993-02-09 |
| 5086407 | Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation | William B. Ledbetter, Jr., Steven C. McMahan, Michael G. Gallup, Russell Stanphill, James G. Gay | 1992-02-04 |
| 5075846 | Memory access serialization as an MMU page attribute | Russell A. Reininger, William B. Ledbetter, Jr., Robin W. Edenfield, Van B. Shahan, Eric Quintana | 1991-12-24 |
| 5029072 | Lock warning mechanism for a cache | William C. Moyer, James G. Gay, Jesse R. Wilson | 1991-07-02 |
| 4723224 | Content addressable memory having field masking | Terry Van Hulett, Jesse R. Wilson | 1988-02-02 |