PY

Pradeep Yadav

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
UC University Of North Carolina At Charlotte: 1 patents #133 of 296Top 45%
📍 Sidhauli, IN: #23 of 386 inventorsTop 6%
Overall (All Time): #826,506 of 4,157,543Top 20%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
11188696 Method, system, and product for deferred merge based method for graph based analysis pessimism reduction Amit Dhuria, Sri Harsha POTHUKUCHI, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra +2 more 2021-11-30
10289774 Systems and methods for reuse of delay calculation in static timing analysis Ratnakar Goyal, Prashant Sethia, Manuj Verma 2019-05-14
9529962 System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design Amit Dhuria, Manuj Verma, Naresh Kumar, Prashant Sethia 2016-12-27
9384310 View data sharing for efficient multi-mode multi-corner timing analysis Igor Keller, Jijun Chen 2016-07-05
8863052 System and method for generating and using a structurally aware timing model for representative operation of a circuit design Amit Dhuria, Naresh Kumar, Umesh Gupta, Prashant Sethia 2014-10-14
4950987 Magneto-inductive sensor for performing tactile and proximity sensing John M. Vranish 1990-08-21